Semiconductor memory apparatus with reduced line widths

  • US 5,375,095 A
  • Filed: 06/12/1991
  • Issued: 12/20/1994
  • Est. Priority Date: 07/06/1990
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory apparatus including a memory array region having formed therein:

  • a plurality of unit memory cell blocks distributed through said memory array region at regular spacings, each formed of an array of memory cells;

    a plurality of unit sense amplifier blocks distributed among said unit memory cell blocks at regular spacings, each formed of an array of sense amplifier circuits;

    a plurality of sense amplifier drive circuits for driving said sense amplifier circuits, distributed among said unit sense amplifier blocks at regular spacings; and

    first and second voltage supply meshes, mutually electrically isolated and each extending throughout said memory array region, respectively coupled to receive first and second supply voltages;

    each of said sense amplifier drive circuits being coupled to an adjacent point on said first voltage supply mesh to receive said first supply voltage and to an adjacent point on said second voltage supply mesh to receive said second supply voltage.

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