Circuit for generating signals in phase quadrature and associated method therefor

• US 5,375,258 A
• Filed: 12/07/1992
• Issued: 12/20/1994
• Est. Priority Date: 12/07/1992
• Status: Expired due to Term

• Current Assignee: Motorola Mobility LLC (Lenovo Group Ltd.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gillig, Steven F.
• Primary Examiner(s): Urban, Edward F.
• Assistant Examiner(s): LIN, MARY
• Application Number:
  US07/986,206
• Time in Patent Office: 743 Days
• Field of Search: 455/209, 455/207, 455/208, 455/318, 455/319, 455/317, 455/316, 455/118, 455/86, 455/87, 375/39, 375/94, 375/81, 332/127
• US Class Current: 455/87
• CPC Class Codes: H03B 2200/0064 Pulse width, duty cycle or on/off ratio
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H04B 1/408 the transmitter oscillator frequency being identical to the receiver local oscillator frequency

Abstract

A quadrant generator for generating a pair of pulse trains maintained in perfect phase quadrant with one another. The quadrature generator includes a feedback control loop for altering the duty cycle of an oscillating signal applied to a master-slave flip-flop pair configured to generate a pair of pulse trains maintained in a relative phase relationship. The feedback control loop controls the duty cycle of the oscillating signal applied to the master-slave flip-flop pair which, in turn, is determinative of the phase relationship between the pulse train pair generated by the master-slave flip-flop pair. When the pulse trains generated by the flip-flop pair are beyond phase quadrature, a control signal generated by the feedback control loop alters the duty cycle of the oscillating signal applied to the flip-flop pair to alter the phase relationship between the pulse trains of the pulse train pair.

Claims

1. A circuit for generating a set of signals maintained in phase quadrature with one another responsive to application of a clock signal defined by a clock signal duty cycle thereto, said circuit comprising:

an oscillator circuit to generate an oscillating signal having an oscillating signal duty cycle, the oscillator circuit coupled to receive the clock signal and operative responsive to values thereof;

a pulse generator to generate a pulse train-pair comprised of a first pulse train and a second pulse train wherein the first pulse train and the second pulse train are at substantially the same frequency but offset in phase relative to one another, the generator coupled to receive the oscillating signal generated by the oscillator circuit; and

a feedback control circuit coupled to receive signals representative of phases of the first and second pulse trains, respectively, and coupled to the oscillator circuit, the feedback control circuit having a phase determining circuit to determine relative phase differences between the phases of the first and second pulse trains and to generate a control signal representative of the relative phase differences between the first and second pulse trains for application to the oscillator circuit, wherein the oscillator circuit alters the duty cycle of the oscillating signal when the first and second pulse trains are beyond phase quadrature with one another, thereby to position and maintain the first and second pulse trains in phase quadrature with one another.

2. A circuit for generating a set of signals maintained in phase quadrature with one another, the circuit comprising:

a clock oscillator for generating a clock signal defined by a clock signal duty cycle;

a duty cycle adjuster having a first input and a second input wherein the first input is coupled to receive the clock signal, the duty cycle adjuster for generating an oscillating signal defined by an oscillating signal duty cycle;

a phase-offset signal generator coupled to receive the oscillating signal generated by the duty cycle adjuster, the phase-offset signal generator for generating a pulse train-pair comprised of a first pulse train and a second pulse train wherein the first pulse train and the second pulse train are at substantially the same frequency but offset in phase relative to one another; and

a feedback detector coupled to receive signals representative of phases of the first and second pulse trains, respectively, the feedback detector for determining relative phase differences between the phases of the first and second pulse trains and for generating a control signal representative of the relative phase differences for application to the second input of the duty cycle adjuster, the duty cycle adjuster responsive to the control signal representative of the relative phase difference to alter the duty cycle of the oscillating signal when the first and second pulse trains are beyond phase quadrature with one another, the feedback detector thereby forming a feedback control loop to position and maintain first and second pulse trains in phase quadrature with one another.

3. The circuit of claim 2 wherein the clock oscillator comprises a phase-locked oscillator of a desired oscillation frequency.

4. The circuit of claim 3 wherein the clock oscillator further comprises a frequency doubler coupled to the phase-locked oscillator, the frequency doubler for generating an output signal comprising the clock signal of a frequency twice the oscillation frequency.

5. The circuit of claim 2 wherein the duty cycle adjuster comprises a comparator circuit defining a threshold level alterable responsive to values of the control signal generated by the feedback detector, the comparator circuit for generating an output signal of a first level when the clock signal is of a value above the threshold level and of a second level when the clock signal is of a value below the threshold level, the output signal formed thereby forming the oscillating signal defined by the oscillating signal duty cycle, whereby values of the threshold level defined by the comparator circuit are determinative of the oscillating signal duty cycle.

6. The circuit of claim 5 further comprising an average value detector coupled to receive the clock signal generated by the clock oscillator, the average value detector for determining the average value of the clock signal and for generating a signal indicative of the average value determined thereat, and an altering circuit for altering the signal indicative of the average value of the clock signal responsive to values of the control signal generated by the feedback-loop detector thereby forming an altered, average-value signal for application to the second input of the duty cycle adjuster.

7. The circuit of claim 5 further comprising an altering circuit for altering the clock signal responsive to values of the control signal generated by the feedback-loop detector thereby forming an altered clock signal for application to the first input of the duty cycle adjuster.

8. The circuit of claim 7 further comprising an inverter coupled to receive the clock signal generated by the clock oscillator, the inverter for inverting the clock signal to form an inverted clock signal thereby, and means for altering the inverted clock signal responsive to values of the control signal thereby forming an altered, inverted clock signal for application to the second input of the duty cycle adjuster.

9. The circuit of claim 2 wherein the phase-offset signal generator is comprised of a pair of flip-flops wherein an output line of a first flip-flop of the pair of flip-flops is coupled to an input of a second flip-flop of the pair of flip-flops and an output line of the second flip-flop is coupled to an input of the first flip-flop, and wherein the oscillating signal generated by the duty cycle adjuster is supplied to a clock input of the first flip-flop and to an inverted clock input of the second flip-flop, whereby signals generated upon the output lines of the first and second flip-flops, respectively, are offset in phase relative to one another by phase differences corresponding to values of the oscillating signal duty cycle of the oscillating signal.

10. The circuit of claim 2 wherein the feedback detector is coupled to receive the oscillating signal generated by the duty cycle adjuster.

11. The circuit of claim 10 wherein the feedback detector comprises a comparator circuit coupled to receive the oscillating signal generated by the duty cycle adjuster and operative to generate an output signal of a first level when the oscillating signal is above a threshold level of the comparator circuit and of a second level when the oscillating signal is of a value below the threshold level of the comparator circuit.

12. The circuit of claim 11 wherein the feedback detector further comprises an integrator circuit coupled to receive the output signal generated by the comparator circuit, the integrator circuit for determining an average value of the output signal supplied thereto and for generating a signal comprising the control signal representative of the average value determined thereat for application to the second input of the duty cycle adjuster.

13. The circuit of claim 11 wherein the feedback detector further comprises a filter circuit coupled to receive the output signal generated by the comparator circuit, the filter circuit for generating a filtered signal, and an amplifier coupled to receive the filtered signal generated by the filter circuit, the amplifier for amplifying the filtered signal to form an amplified signal thereby, the amplified signal comprising the control signal for application to the second input of the duty cycle adjuster.

14. The circuit of claim 2 wherein said feedback detector is coupled to receive the first pulse train and the second pulse train of the pulse train-pair generated by the phase-offset signal generator.

15. A circuit for generating a set of signals maintained in phase quadrature with one another, the circuit comprising:

a clock oscillator for generating a clock signal defined by a clock signal duty cycle;

a duty cycle adjuster having a first input and a second input wherein the first input is coupled to receive the clock signal at the first input thereof, the duty cycle adjuster for generating an oscillating signal defined by an oscillating signal duty cycle;

a phase-offset signal generator coupled to receive the oscillating signal generated by the duty cycle adjuster, the phase-offset signal generator for generating a pulse train-pair comprised of a first pulse train and a second pulse train wherein the first pulse train and the second pulse train are at substantially the same frequency but offset in phase relative to one another; and

a feedback detector coupled to receive signals representative of phases of the first and second pulse trains, respectively, the feedback detector for determining relative phase differences between the phases of the first and second pulse trains and for generating a control signal representative of the relative phase differences for application to the second input of the duty cycle adjuster, the duty cycle adjuster responsive to the control signal representative of the relative phase difference to alter the duty cycle of the oscillating signal when the first and second pulse trains are beyond phase quadrature with one another, the feedback detector thereby forming a feedback control loop to position and maintain first and second pulse trains in phase quadrature with one another;

wherein the feedback detector is coupled to receive the first pulse train and the second pulse train of the pulse train-pair generated by the phase-offset signal generator; and

wherein the feedback detector comprises an exclusive-or logic gate having a first input and a second input wherein the first pulse train is applied to the first input of the exclusive-or logic gate and wherein the second pulse train is applied to the second input of the exclusive-or logic gate.

16. The circuit of claim 15 wherein the feedback detector further comprises an integrator circuit coupled to an output of the exclusive-or logic gate, the integrator circuit for determining an average value of a signal generated at the output of the exclusive-or logic gate and for generating a signal comprising the control signal for application to the second input of the duty cycle adjuster.

17. A method for converting a clock signal generated by a clock oscillator into a set of signals maintained in phase quadrature with one another, said method comprising the steps of:

applying the clock signal to a first input of a duty cycle adjuster;

generating an oscillating signal defined by an oscillating signal duty cycle at an output of the duty cycle adjuster;

applying the oscillating signal generated during the step of generating the oscillating signal to a phase-offset signal generator;

generating a pulse train-pair comprised of a first pulse train and a second pulse train at outputs of the phase-offset signal generator wherein the first pulse train and the second pulse train are of similar frequencies but offset in phase relative to one another;

determining relative phase differences between phases of the first and second pulse trains generated during the step of generating the pulse train pair;

generating a control signal representative of relative phase differences between the phases of the first and second pulse trains;

applying the control signal generated during said step of generating the control signal to a second input of the duty cycle adjuster; and

altering the oscillating signal duty cycle of the oscillating signal generated by the duty cycle adjuster when the first and second pulse trains are beyond phase quadrature with one another, thereby to position and maintain the first and second pulse trains in phase quadrature with one another.

18. In a receiver operative to receive a modulated signal transmitted thereto and having frequency conversion circuitry for down-converting the modulated signal into a down-converted signal, a combination with the frequency conversion circuitry of a quadrature mixer for converting the down-converted signal into a pair of signals in phase quadrature with one another, the quadrature mixer comprising:

a clock oscillator for generating a clock signal defined by a clock signal duty cycle;

a duty cycle adjuster having a first input and a second input wherein the first input is coupled to receive the clock signal at the first input thereof, the duty cycle adjuster for generating an oscillating signal defined by an oscillating signal duty cycle;

a phase-offset signal generator coupled to receive the oscillating signal generated by the duty cycle adjuster, the phase-offset signal generator for generating a pulse train-pair comprised of a first pulse train and a second pulse train wherein the first pulse train and the second pulse train are of similar frequencies but offset in phase relative to one another;

a feedback detector coupled to receive a signal representative of phases of the first and second pulse trains, respectively, the feedback detector for determining relative phase differences between the phases of the first and second pulse trains and for generating a control signal representative of the relative phase differences for application to the second input of the duty cycle adjuster whereat the duty cycle adjuster alters the oscillating signal duty cycle of the oscillating signal when the first and second pulse trains are beyond phase quadrature with one another, the feedback detector thereby forming a feedback control loop to position and maintain first and second pulse trains in phase quadrature with one another;

a first mixer coupled to receive the down-converted signal and the first pulse train, the first mixer for generating a first mixed signal formed of the down-converted signal and the first pulse train; and

a second mixer coupled to receive the down-converted signal and the second pulse train, the second mixer for generating a second mixed signal formed of the down-converted signal and the second pulse train whereby the second mixed signal is in phase quadrature with the first mixed signal.

19. The combination in the receiver of claim 18 wherein the feedback detector is coupled to receive the oscillating signal generated by the duty cycle adjuster.

20. The combination in the receiver of claim 18 wherein the feedback-loop detector is coupled to receive the pulse train-pair comprised of the first pulse train and the second pulse train generated by the phase-offset signal generator.

21. In a transmitter operative to transmit a communication signal and having modulation circuitry for modulating the communication signal to form first and second modulated signals, a combination with the modulation circuitry of a quadrature mixer for converting the first and second modulated signals into first and second up-converted signals, respectively, said quadrature mixer comprising:

a clock oscillator for generating a clock signal defined by a clock signal duty cycle;

a duty cycle adjuster having a first input and a second input wherein the first input is coupled to receive the clock signal at the first input thereof, the duty cycle adjuster for generating an oscillating signal defined by an oscillating signal duty cycle;

a phase-offset signal generator coupled to receive the oscillating signal generated by the duty cycle adjuster, the phase-offset signal generator for generating a pulse train-pair comprised of a first pulse train and a second pulse train wherein the first pulse train and the second pulse train are of similar frequencies but offset in phase relative to one another;

a feedback detector coupled to receive a signal representative of phases of the first and second pulse trains, respectively, the feedback detector for determining relative phase differences between the phases of the first and second pulse trains and for generating a control signal representative of the relative phase differences for application to the second input of the duty cycle adjuster whereat the duty cycle adjuster alters the oscillating signal duty cycle of the oscillating signal when the first and second pulse trains are beyond phase quadrature with one another, the feedback detector thereby forming a feedback control loop to position and maintain first and second pulse trains in phase quadrature with one another;

a first mixer coupled to receive the first modulated signal and the first pulse train, the first mixer for generating a first mixed signal comprising the first up-converted signal formed of the first modulated signal and the first pulse train; and

a second mixer coupled to receive the second modulated signal and the second pulse train, the second mixer for generating a second mixed signal comprising the second up-converted signal formed of the modulated signal and the second pulse train.