Memory control unit with selective execution of queued read and write requests

  • US 5,379,379 A
  • Filed: 09/06/1990
  • Issued: 01/03/1995
  • Est. Priority Date: 06/30/1988
  • Status: Expired due to Term
First Claim
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1. A memory control unit for controlling a main system memory of a data processing system, the main system memory being comprised of at least one memory unit, comprising:

  • first interface means for coupling said memory control unit to the at least one memory unit of the main system memory;

    second interface means for coupling said memory control unit to a system bus having signal lines for expressing information units, including memory read and write requests, the system bus including a system address bus;

    means, coupled to said first and to said second interface means and responsive to a write request from said system bus, for executing the write request by storing one or more information units within a memory unit at an address specified by the system address bus, said write request executing means comprising write request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received write requests and associated write addresses prior to execution of the write requests;

    means, coupled to said first and to said second interface means and responsive to a read request from said system bus, for executing the read request by reading one or more information units from a memory unit at a location specified by the system address bus, said read request executing means comprising read request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received read requests and associated read addresses prior to execution of the read requests;

    said memory control unit further comprising;

    means, having a first input coupled to said write buffer means and a second input coupled to said read request receiving means, for comparing a received read address to write addresses stored in said write address buffer means, said comparing means having an output signal for indicating, when asserted, an occurrence of the reception of a read address within a predetermined range of addresses of one of said stored write addresses; and

    means for controlling the execution of read and write requests, said controlling means being coupled to said comparing means output signal and being responsive to said comparing means output signal not being asserted for causing an execution of all buffered read requests before any buffered write requests, said controlling means further being responsive to said comparing means output signal being asserted for first causing an execution of only those buffered read requests which precede a buffered read request which caused the assertion of said comparing means output signal and then causing an execution of buffered write requests.

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