Memory control unit with selective execution of queued read and write requests

• US 5,379,379 A
• Filed: 09/06/1990
• Issued: 01/03/1995
• Est. Priority Date: 06/30/1988
• Status: Expired due to Term

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: Wang Laboratories Incorporated
• Inventors: Becker, Robert D., Curcuru, Kevin H., Eng, Kenneth J., Schwartz, Martin J.
• Primary Examiner(s): Black, Thomas G.
• Assistant Examiner(s): Von Buhr, Maria N.
• Application Number:
  US07/580,365
• Time in Patent Office: 1,580 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 395/250, 395/425, 395/650, 395/725
• US Class Current: 711/3
• CPC Class Codes: G06F 13/1631 through address comparison

Abstract

A memory control unit (MCU) 22 includes a first interface for interfacing the memory control unit to one or more memory units; a second interface for interfacing the memory control unit to a system bus, including a system data bus for expressing information units, including memory read and write requests, and a system address bus. The MCU further includes logic, responsive to a write request from the system bus, for storing one or more information units within a memory unit at an address specified by the system address bus. The storing logic includes write request receiving and buffer logic having a plurality of storage locations for storing received write requests and associated write addresses prior to the execution of the write requests. The MCU further includes logic, responsive to a read request from the system bus, for reading one or more information units from a memory unit at a location specified by the system address bus. The reading logic includes read request receiving and buffer logic having a plurality of storage locations for storing received read requests and associated read addresses prior to the execution of the read requests. The memory control unit further has logic for comparing a received read address to write addresses stored in the write address buffer, the comparing logic having an output for indicating, when asserted, the occurence of the reception of a read address having a value within a predetermined range of values of one of the stored write addresses.

Claims

1. A memory control unit for controlling a main system memory of a data processing system, the main system memory being comprised of at least one memory unit, comprising:

first interface means for coupling said memory control unit to the at least one memory unit of the main system memory;

second interface means for coupling said memory control unit to a system bus having signal lines for expressing information units, including memory read and write requests, the system bus including a system address bus;

means, coupled to said first and to said second interface means and responsive to a write request from said system bus, for executing the write request by storing one or more information units within a memory unit at an address specified by the system address bus, said write request executing means comprising write request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received write requests and associated write addresses prior to execution of the write requests;

means, coupled to said first and to said second interface means and responsive to a read request from said system bus, for executing the read request by reading one or more information units from a memory unit at a location specified by the system address bus, said read request executing means comprising read request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received read requests and associated read addresses prior to execution of the read requests;

said memory control unit further comprising;

means, having a first input coupled to said write buffer means and a second input coupled to said read request receiving means, for comparing a received read address to write addresses stored in said write address buffer means, said comparing means having an output signal for indicating, when asserted, an occurrence of the reception of a read address within a predetermined range of addresses of one of said stored write addresses; and

means for controlling the execution of read and write requests, said controlling means being coupled to said comparing means output signal and being responsive to said comparing means output signal not being asserted for causing an execution of all buffered read requests before any buffered write requests, said controlling means further being responsive to said comparing means output signal being asserted for first causing an execution of only those buffered read requests which precede a buffered read request which caused the assertion of said comparing means output signal and then causing an execution of buffered write requests.

2. A memory control unit as defined in claim 1 wherein said controlling means further comprises means coupled to said second interface means and responsive to the assertion of said comparing means output signal for preventing a reception of any further read or write requests from said system bus until the execution of all buffered write requests.

3. A memory control unit as defined in claim 1 and further comprising:

means, coupled to said second interface means and responsive to an execution of a read request, for returning one or more information units to said system bus; and

error detection and correction means for detecting and correcting a single bit error in an information unit returned to said system bus, thereby generating a corrected information unit, and including means for subsequently providing the corrected information unit to said returning means.

4. A memory control unit as defined in claim 3 wherein:

said second interface means comprises means for requesting and receiving access to said system bus; and

said returning means is responsive to the operation of said second interface means for returning an information unit to said system bus prior to a completion of the operation of said error detection and correction means, said returning means being coupled to said error detection and correction means for receiving a corrected information unit therefrom for returning the corrected information unit to said system bus at a time subsequent to a time when an information unit having a single bit error is returned to said system bus.

5. A memory control unit as defined in claim 4 wherein said returning means comprises means for indicating on said system bus that an information unit being returned has a bit in error.

6. A memory control unit as defined in claim 3 wherein said error detection and correction means further comprises means for detecting multiple bit errors in an information unit returned to said system bus, and wherein said returning means further comprises means for indicating on said system bus that an information unit being returned has more than one bit in error.

7. In an information processing system having a system bus for coupling together a plurality of bus connections, one of the bus connections being a memory control unit coupled to one or more memory units, the memory control unit being responsive to address and data signal lines of the system bus for writing information units to and for reading information units from the memory units, a method of reading and writing the information units comprising the steps of:

buffering write requests, including write addresses, as they are received from the system bus;

buffering read requests, including read addresses, as they are received from the system bus;

comparing when received each read address against buffered write addresses, if any, to determine if a received read address has an address value within a predetermined range of address values of a buffered write address;

if a received address is determined not to be within the predetermined range of addresses of any buffered write addresses then;

first executing in sequence all buffered read requests; and

then executing in sequence all buffered write requests;

else if a received address is determined to have an address value within the predetermined range of address values of any buffered write address;

first executing in sequence all buffered read requests up to but not including the received read request which was determined to be within the predetermined range;

then executing all buffered write requests; and

then executing the buffered read request which was determined to be within the predetermined range.

8. The method of claim 7 wherein the first step of executing when a received read address is determined to be within the predetermined range of addresses includes an initial step of asserting a system bus signal which prevents other bus connections from issuing any further read requests or write requests.

9. The method of claim 7 wherein the steps of executing in sequence all buffered read requests are accomplished by:

applying a read address to the memory units;

retrieving an information unit from a memory unit storage location corresponding to the applied read address;

applying, during a first interval of time, the retrieved information unit to an error detection and correction unit to determine if the retrieved information unit has at least one bit in error, the error detection and correction unit further including means for correcting a single bit error in the retrieved information unit; and

driving, during the first interval of time, the retrieved information unit onto the system bus data lines.

10. The method of claim 9 wherein if the error detection and correction unit indicates that the retrieved information unit has a bit in error further comprises the steps of:

asserting a system bus signal for indicating that the retrieved information unit has a bit in error; and

driving during a second, later interval of time the corrected information unit onto the system bus data lines.

11. The method of claim 9 wherein if the error detection and correction unit indicates that the retrieved information unit has more than one bit in error further comprises a step of asserting a system bus signal for indicating an error condition.

12. The method of claim 11 wherein if a received read or write address has a value which exceeds a predetermined maximum value further includes a step of asserting the system bus signal that indicates the error condition.

13. A memory control unit for controlling a main system memory of a data processing system, the main system memory being comprised of at least one memory unit, comprising:

first interface means for coupling said memory control unit to the at least one memory unit of the main system memory;

second interface means for coupling said memory control unit to a system bus having signal lines for expressing information units, including memory read and write requests, the system bus including a system address bus;

means, coupled to said first and to said second interface means and responsive to a write request from said system bus, for executing the write request by storing one or more information units within a memory unit at an address specified by the system address bus, said write request executing means comprising write request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received write requests and associated write addresses prior to execution of the write requests;

means, coupled to said first and to said second interface means and responsive to a read request from said system bus, for executing the read request by reading one or more information units from a memory unit at a location specified by the system address bus, said read request executing means comprising read request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received read requests and associated read addresses prior to execution of the read requests;

said memory control unit further comprising;

means, having a first input coupled to said write buffer means and a second input coupled to said read request receiving means, for comparing a received read address to write addresses stored in said write address buffer means, said comparing means having an output signal for indicating, when asserted, an occurrence of the reception of a read address within a predetermined range of addresses of one of said stored write addresses, the comparing means output being coupled to means for controlling an order of execution of stored read requests and stored write requests as a function of whether the comparing means output signal is asserted or is not asserted; and

means for decoding said read requests to determine a type of read request, said decoding means having an out coupled to said comparing means for determining a number of bits of said read address which are compared to the buffered write addresses, the number of bits being determined as a function of the type of read request.

14. A memory control unit as defined in claim 13 wherein said decoding means is responsive to read requests for determining if one of said read requests is associated with a first type of request which reads data from a location within said memory control unit, a second type of read request which reads an octal word of data from a memory unit, a third type of read request which reads a quad word from one of a memory unit, or a fourth type of read request which reads at least a double word from a memory unit.

15. A memory control unit as defined in claim 14 wherein said comparing means compares four bits when said decoding means determines that a read request is associated with said first type of read request.

16. A memory control unit as defined in claim 14 wherein said comparing means compares ten bits when said decoding means determines that a read request is associated with said second type of read request.

17. A memory control unit as defined in claim 14 wherein said comparing means compares eleven bits when said decoding means determines that a read request is associated with said third type of read request.

18. A memory control unit as define in claim 14 wherein said comparing means compares twelve bits when said decoding means determines that a read request is associated with said fourth type of read request.

19. A memory control unit for controlling a main system memory of a data processing system, the main system memory being comprised of at least one memory unit, comprising:

first interface means for coupling said memory control unit to the at least one memory unit of the main system memory;

second interface means for coupling said memory control unit to a system bus having signal lines for expressing information units, including memory read and write requests, the system bus including a system address bus;

means, coupled to said first and to said second interface means and responsive to a write request from said system bus, for executing the write request by storing one or more information units within a memory unit at an address specified by the system address bus, said write request executing means comprising write request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received write requests and associated write addresses prior to execution of the write requests;

means, coupled to said first and to said second interface means and responsive to a read request from said system bus, for executing the read request by reading one or more information units from a memory unit at a location specified by the system address bus, said read request executing means comprising read request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received read requests and associated read addresses prior to execution of the read requests;

said memory control unit further comprising;

means, having a first input coupled to said write buffer means and a second input coupled to said read request receiving means, for comparing a received read address to write addresses stored in said write address buffer means, said comparing means having an output signal for indicating, when asserted, an occurrence of the reception of a read address within a predetermined range of addresses of one of said stored write addresses, the comparing means output being coupled to means for controlling an order of execution of stored read requests and stored write requests as a function of whether the comparing means output signal is asserted or is not asserted; and

means, having an input coupled to said comparing means output signal and an output coupled to said system bus for asserting a signal on said system bus when said comparing means output signal is asserted, said signal preventing a reception of further read or write requests from said system bus.

20. A memory control unit for controlling a main system memory of a data processing system, the main system memory being comprised of at least one memory unit, comprising:

first interface means for coupling said memory control unit to the at least one memory unit of the main system memory;

second interface means for coupling said memory control unit to a system bus having signal lines for expressing information units, including memory read and write requests, the system bus including a system address bus;

means, coupled to said first and to said second interface means and responsive to a write request from said system bus, for executing the write request by storing one or more information units within a memory unit at an address specified by the system address bus, said write request executing means comprising write request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received write requests and associated write addresses prior to execution of the write requests;

means, coupled to said first and to said second interface means and responsive to a read request from said system bus, for executing the read request by reading one or more information units from a memory unit at a location specified by the system address bus, said read request executing means comprising read request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received read requests and associated read addresses prior to execution of the read requests;

means, having a first input coupled to said write buffer means and a second input coupled to said read request receiving means, for comparing a received read address to write addresses stored in said write address buffer means, said comparing means having an output signal for indicating, when asserted, an occurrence of the reception of a read address within a predetermined range of addresses of one of said stored write addresses, the comparing means output being coupled to means for controlling an order of execution of stored read requests and stored write requests as a function of whether the comparing means output signal is asserted or is not asserted; and

said memory control unit further comprising;

means for returning, in response to an execution of a read request, at least one information unit to said system bus;

means, having an input coupled to said read request executing means, for determining during a time that an information unit is returned to said system bus if one or more bits of the information unit read from a memory unit is in error, the determining

means further including means for correcting a single bit error in an information unit for providing to said returning means a corrected information unit to be subsequently returned to said system bus; and

means, having an input coupled to said determining means and an output coupled to said system bus, for asserting a first signal on said system bus when said determining means determines that an information unit has one bit in error.

21. A memory control unit as defined in claim 20 wherein said asserting means is operable for asserting a second signal on said system bus, said second signal being asserted when said determining means determines that an information unit has more than one bit in error.

22. A memory control unit for controlling a main system memory of a data processing system, the main system memory being comprised of at least one memory unit, comprising:

first interface means for coupling said memory control unit to the at least one memory unit of the main system memory;

second interface means for coupling said memory control unit to a system bus having signal lines for expressing information units, including memory read and write requests, the system bus including a system address bus;

means, coupled to said first and to said second interface means and responsive to a write request from said system bus, for executing the write request by storing one or more information units within a memory unit at an address specified by the system address bus, said write request executing means comprising write request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received write requests and associated write addresses prior to execution of the write requests;

means, coupled to said first and to said second interface means and responsive to a read request from said system bus, for executing the read request by reading one or more information units from a memory unit at a location specified by the system address bus, said read request executing means comprising read request receiving and buffer means having a plurality of storage locations capable of storing a plurality of received read requests and associated read addresses prior to execution of the read requests;

said memory control unit further comprising;

means responsive to the operation of said write request receiving and buffer means and to said read request executing means for determining, at least during a time that said read request executing means is executing a buffered read request, when a predetermined number of write requests are buffered within said write request buffer means, the predetermined number being less than a maximum possible number of buffered write requests;

means responsive to the operation of said determining means for causing said second interface means to assert a signal on said system bus when said determining means determines that the predetermined number of write requests are buffered within said write request buffer means, an assertion of said signal preventing a reception of further read or write requests from said system bus; and

means responsive to the operation of said determining means for executing at least one buffered write request such that the remaining number of buffered write requests is less than the predetermined number.

23. A memory control unit as set forth in claim 22 and further comprising means, having a first input coupled to said write buffer means and a second input coupled to said read request receiving means, for comparing a received read address to write addresses stored in said write address buffer means, said comparing means having an output signal for indicating, when asserted, an occurrence of the reception of a read address within a range of addresses of one of said stored write addresses, said memory control unit further comprising means for controlling the execution of read and write requests, said controlling means being coupled to said comparing means output signal and being responsive to said comparing means output signal not being asserted for causing an execution of all buffered read requests before any buffered write requests, said controlling means further being responsive to said comparing means output signal being asserted for causing an execution of only those buffered read requests which precede a buffered read request which caused the assertion of said comparing means output signal and then causing an execution of buffered write requests.

24. A memory control unit coupled between a system bus and a main system memory for controlling the operation of the main system memory, the system bus being comprised of address signal lines for specifying addresses within the main system memory, data signal lines for conveying data units between bus connections coupled to the system bus and the main system memory, and at least one signal line for specifying whether a particular system bus transaction initiated by one of the bus connections is a main system memory read request or a main system memory write request, the memory control unit comprising:

means coupled to the system bus for receiving main system memory read requests and main system memory write requests therefrom;

means coupled to the main system memory for executing main system memory read requests and main system memory write requests;

means coupled to the receiving means for buffering a plurality of main system memory write requests, including a main system memory write address associated with each main system memory write request, prior to execution of main system memory write requests;

means coupled to the receiving means for buffering a plurality of main system memory read requests, including a main system memory read address associated with each main system memory read request, prior to execution of main system memory read requests;

means having a first input coupled to the receiving means and a second input coupled to the means for buffering main system memory write requests for comparing a received main system memory read address against all buffered main system memory write addresses, if any, to determine if a received main system memory read address has an address value within a predetermined range of address values of one of the buffered main system memory write addresses, the comparing means including means for asserting an output signal for indicating that a received main system memory read address has an address value within the predetermined range of address values of one of the buffered main system memory write addresses; and

wherein

the executing means has an input coupled to the comparing means output signal and is responsive to an assertion thereof for first executing in order as received all buffered main system memory read requests up to but not including the main system memory read request which was determined to be within the predetermined range of address values, then executing in order as received buffered main system memory write requests, and then executing the buffered main system memory read request which was determined to be within the predetermined range of address values.

25. A memory control unit as set forth in claim 24 wherein the comparing means includes means for executing an associative comparison between each received system memory read address and all buffered system memory write addresses, if any, to determine if the received system memory read address has an address value within a predetermined range of address values of one of the buffered system memory write addresses, the associative comparison means having an output coupled to said asserting means.

26. A memory control unit as set forth in claim 24 and further comprising:

means coupled to the system memory write request buffering means for determining when a predetermined number of system memory write requests are buffered within the system memory write request buffering means, the predetermined number being less than a maximum capacity of the system memory write request buffering means;

means responsive to the operation of the predetermined number determining means for asserting a signal on the system bus when the predetermined number determining means determines that the predetermined number of system memory write requests are buffered, an assertion of the system bus signal preventing bus connections from issuing further system memory read or system memory write requests on the system bus; and

wherein

the executing means is coupled to and is responsive to the operation of the predetermined number determining means for executing at least one buffered system memory write request such that the remaining number of buffered system memory write requests is less than the predetermined number.