Stacked high voltage transistor unit

• US 5,382,826 A
• Filed: 12/21/1993
• Issued: 01/17/1995
• Est. Priority Date: 12/21/1993
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Vo, Tuan A., Mojaradi, Mohamad M.
• Primary Examiner(s): Loke, Steven Ho Yin
• Application Number:
  US08/170,848
• Time in Patent Office: 392 Days
• Field of Search: 257/488, 257/489, 257/491, 257/409, 257/379, 257/380, 257/536, 257/538, 257/341, 307/575, 307/577, 307/584, 307/248
• US Class Current: 257/489
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/102 in field-effect transistor switches

Abstract

A high current, high voltage transistor which can be easily electrically stacked to extend the voltage range and uses less silicon area than a conventional stacked transistor configuration and a configuration of field plates that provide the greatest breakdown voltages with the highest ohmic values. Also, a star shaped field plate design which provides the greatest breakdown voltages with the highest ohmic values. The field plate is constructed using several concentric rings connected by fingers that are wider at towards the center of the concentric rings and narrower towards the perimeter of the concentric rings.

Claims

1. A high voltage cascaded network circuit comprising:

a) an electrical circuit of two four terminal high voltage transistors, one of the two transistors being a first transistor in the electrical circuit and the other transistor being a second transistor in the electrical circuit, each transistor comprising;

i) a source region, a drain region, a gate region, and a resistor region,

ii) said drain region, said resistor region, said gate region, and said source region being arranged in a concentric configuration with said drain region being the innermost region, said resistor region surrounding said drain region, said gate region surrounding said resistor region, and said source region surrounding said gate region,

iii) a source having a source terminal, said source being located in said source region,

iv) a drain having a drain terminal, said drain being located in said drain region,

v) a gate having a gate terminal, said gate being located in said gate region,

vi) a resistor terminal, and

vii) a resistor means having two ends, said resistor means being located in said resistor region, one end of said resistor means being electrically connected to said gate terminal and the other end of said resistor means being electrically connected to said resistor terminal,

b) a positive node,

c) a negative node,

d) said source terminal of said first transistor being electrically connected to said negative node,

e) said resistor terminal and said drain terminal of said second transistor being electrically connected to said positive node,

f) said drain terminal of said first transistor being electrically connected to said source terminal of said second transistor, and

g) said resistor terminal of said first transistor being electrically connected to said gate terminal of said second transistor.

2. A high voltage cascaded network circuit comprising:

a) an electrical circuit of a plurality of four terminal high voltage transistors electrically connected to each other in a sequential order, one of said transistors being a first transistor in the electrical circuit and another of said transistors being a last transistor in the electrical circuit, each transistor comprising;

i) a source region, a drain region, a gate region, and a resistor region,

ii) said drain region, said register region, said gate region, and said source region being arranged in a concentric configuration with said drain region being the innermost region, said resistor region surrounding said drain region, said gate region surrounding said resistor region, and said source region surrounding said gate region,

iii) a source having a source terminal, said source being located in said source region,

iv) a drain having a drain terminal, said drain being located in said drain region,

v) a gate having a gate terminal, said gate being located in said gate region,

vi) a resistor terminal, and

vii) a resistor means having two ends, said resistor means

being located in said resistor region, one end of said resistor means being electrically connected to said gate terminal and the other end of said resistor means being electrically connected to said resistor terminal,

b) a positive node,

c) a negative node,

d) said source terminal of said first transistor being electrically connected to said negative node,

e) said resistor terminal and said drain terminal of said last transistor being electrically connected to said positive node, and

f) each of said transistors other than said first and said last transistors having;

i) its drain terminal electrically connected to said source terminal of its respective succeeding transistor in said sequential order,

ii) its resistor terminal electrically connected to said gate terminal of its respective succeeding transistor in said sequential order,

iii) its source terminal electrically connected to said drain terminal of its respective preceeding transistor in said sequential order, and

iv) its gate terminal electrically connected to said resistor terminal of its respective preceeding transistor in said sequential order.

3. A high voltage cascaded network circuit comprising:

a) an electrical circuit of n+1 four terminal high voltage transistors, n being an integer of at least two, each of said transistors being uniquely numbered with an integer i between one and n+1 inclusive, said transistor being numbered one being a first transistor in the electrical circuit and said transistor numbered n+1 being a last transistor in the electrical circuit, each transistor comprising;

i) a source region, a drain region, a gate region, and a resistor region,

ii) said drain region, said resistor region, said gate region and said source region being arranged in a concentric configuration with said drain region being the innermost region, said resistor region surrounding said drain region, said gate region surrounding said resistor region, and said source region surrounding said gate region,

iii) a source having a source terminal, said source being located in said source region,

iv) a drain having a drain terminal, said drain being located in said drain region,

v) a gate having a gate terminal, said gate being located in said gate region,

vi) a resistor terminal, and

vii) a resistor means having two ends, said resistor means being located in said resistor region, one end of said resistor means being electrically connected to said gate terminal and the other end of said resistor means being electrically connected to said resistor terminal,

b) a positive node,

c) a negative node,

d) said source terminal of said first transistor being electrically connected to said negative node,

e) said resistor terminal and said drain terminal of said drain of said last transistor being electrically connected to said positive node, and

f) each of said number i transistors where i is every integer starting with 1 up through n, having;

its drain terminal electrically connected to said source terminal of said transistor numbered (i+1) in the electrical circuit, and

ii) its resistor terminal electrically connected to said gate terminal of said transistor numbered (i+1) in the electrical circuit.