Stacked high voltage transistor unit

  • US 5,382,826 A
  • Filed: 12/21/1993
  • Issued: 01/17/1995
  • Est. Priority Date: 12/21/1993
  • Status: Expired due to Term
First Claim
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1. A high voltage cascaded network circuit comprising:

  • a) an electrical circuit of two four terminal high voltage transistors, one of the two transistors being a first transistor in the electrical circuit and the other transistor being a second transistor in the electrical circuit, each transistor comprising;

    i) a source region, a drain region, a gate region, and a resistor region,ii) said drain region, said resistor region, said gate region, and said source region being arranged in a concentric configuration with said drain region being the innermost region, said resistor region surrounding said drain region, said gate region surrounding said resistor region, and said source region surrounding said gate region,iii) a source having a source terminal, said source being located in said source region,iv) a drain having a drain terminal, said drain being located in said drain region,v) a gate having a gate terminal, said gate being located in said gate region,vi) a resistor terminal, andvii) a resistor means having two ends, said resistor means being located in said resistor region, one end of said resistor means being electrically connected to said gate terminal and the other end of said resistor means being electrically connected to said resistor terminal,b) a positive node,c) a negative node,d) said source terminal of said first transistor being electrically connected to said negative node,e) said resistor terminal and said drain terminal of said second transistor being electrically connected to said positive node,f) said drain terminal of said first transistor being electrically connected to said source terminal of said second transistor, andg) said resistor terminal of said first transistor being electrically connected to said gate terminal of said second transistor.

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