Method for testing non-volatile memories

• US 5,383,193 A
• Filed: 09/25/1992
• Issued: 01/17/1995
• Est. Priority Date: 09/25/1992
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Rosendale, Glen A., Payne, James E., Pathak, Saroj
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): CHUNG, PHUNG M
• Application Number:
  US07/951,207
• Time in Patent Office: 844 Days
• Field of Search: 371/21.4, 371/21.1, 371/25.1, 371/10.2, 371/10.3, 371/62, 371/61, 365/201, 395/575, 395/550
• US Class Current: 714/721
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A method is provided for testing a non-programmable non-volatile memory which does not require the writing or erasing of any cells and permits the testing of all normal memory cells. Testing occurs from the device I/O pins and is useful in cases where EPROM memory cells have been bulk erased and placed within an ultraviolet-opaque package. The non-volatile memory is of the type having memory banks of rows and columns. Each bank must have address decoders and means for changing addresses between banks. A separate auxiliary cell or row of cells in a state different from the non-programmed state is provided. An address is supplied for the auxiliary cells and then for the normal cells and the interval between addressing the normal cells and the appearance of an output signal is measured and compared with a predetermined fixed limit. If the limit is exceeded, the address is identified as that of a weak cell whose speed does not meet product specifications. In suitably equipped memories, the addresses of weak cells can be recorded and redundant cell groups substituted as replacements.

Claims

1. A method of testing non-programmed non-volatile memory arrays, the method comprising the steps of:

(a) specifying an address of a memory cell to be tested in a memory array at a known first time, said memory cell being in a first logic state,

(b) specifying an address of an auxiliary memory cell being in a second logic state, said second logic state being distinguishable from the first logic state,

(c) measuring a delay of an output of the specified memory cell being tested, with reference to said known time, the delay associated with the changing of the output from a level associated with the second logic state to a level associated with the first logic state,

(d) comparing said measured delay with a specified maximum acceptable delay,

(e) if said measured delay exceeds said maximum acceptable delay, designating said address of said memory cell as that of a defective memory cell, and

(f) repeating steps (a) through (e) for other memory cell to be tested in said memory array.

2. The method of claim 1 further comprising the steps of providing a single sense amplifier which first reads said specified memory cell then reads said auxiliary memory cell.

3. The method of claim 1 wherein the step (f) comprises:

testing every memory cell in said memory array by specifying the address of every memory cell.

4. A method for testing non-programmed, non-volatile memory cells in a non-volatile memory array of the type having rows and columns of non-volatile memory cells, the method comprising the steps of:

(a) providing a memory array of the type having rows and columns of non-volatile memory cells, and also having an address decoder and at least one array output, every non-programmed, non-volatile memory cell of the memory array being in a first logic state, each memory cell being characterized by a measurable time delay from a first time at which that memory cell is addressed to a second time when an output of the addressed memory cell is produced with a signal level corresponding to said first logic state;

(b) reserving a memory address corresponding to an addressable memory cell outside of the array, the address referred to as an auxiliary cell, the addressed auxiliary cell producing a second logic state;

(c) performing the following steps on each memory cell to be tested;

(i) addressing the auxiliary cell, then

(ii) addressing a memory cell to be tested, and measuring the time delay which characterizes that memory cell, then

(iii) comparing the measurement with a predetermined mined value, and

(iv) if the measurement exceeds the predetermined value, designating the address of said memory cell as that of a weak cell.

5. The method of claim 4 wherein the memory cells are tested in addressable rows, each memory cell in a row producing a separate output, and each row responding to a different address.

6. The method of claim 4 wherein the memory cells are tested in addressable columns, each column of memory cells producing a single output, and each column responding to a different address.

7. The method of claim 4 further including the steps of recording the address of the weak cell and substituting a redundant group of memory cells for a group of memory cells containing the weak cell.

8. A method for testing non-programmed cells in a non-volatile memory having at least two arrays of the type having rows and columns of memory cells, the method comprising the steps of:

providing a memory including first and second arrays of the type having rows and columns of memory cells, each array having an address decoder and at least one array output, the memory including selector means for selecting one array output and presenting the selected array output as a memory output, each memory cell of the first array being in a first memory state, each memory cell of the first array being characterized by a measurable time delay from a first time at which that memory cell is addressed to a second time when an output of the addressed memory cell is produced with a signal level corresponding to said first memory state, each memory cell of the second array being in a second memory state;

addressing a cell in the second memory array while selecting the output of a first array;

then

addressing a memory cell to be tested in the first array while continuing to select the output of the first array;

then

measuring the time delay which characterizes that memory cell;

then

comparing the measurement with a predetermined value, and if the measurement is greater than the predetermined value, returning a weak cell result;

then

repeating these steps for additional memory cells to be tested, continuing from the step of addressing a cell in the second memory array;

then

when testing of the first array is completed, reversing roles of first and second arrays and commencing testing of the second array.

9. The method of claim 8 wherein the memory cells are tested in addressable rows, each memory cell in a row producing a separate output, and each row responding to a different address.

10. The method of claim 8 wherein the memory cells are tested in addressable columns, each column of memory cells producing a single output, and each column responding to a different address.

11. The method of claim 8 further including the steps of recording the address of the weak cell and substituting a redundant group of memory cells for a group of memory cells containing the weak cell.

12. A method for testing a non-volatile memory, the method comprising the steps of:

providing a memory having at least two banks of memory cells arranged in rows and columns, each bank having address decoders connected to rows and columns of said each bank for addressing at least one of said rows and columns of memory cells in that bank and at least one sense amplifier connected to read memory cells in that bank and to produce an output in response to addressing of a memory cell by said address decoders, all memory cells being in an erased state, each memory cell being characterized by a measurable time delay from a first time at which that memory cell is addressed by said address decoders to a second time when an output of the addressed memory cell is produced by said sense amplifier, the address decoders being disabled so that no row or column is addressed, and the memory having an output selector for selecting the output of each bank'"'"'s at least one sense amplifier for output as a memory output; and

performing the following steps in sequence until testing is completed;

disabling the address decoders and selecting the sense amplifier output of a first memory bank,

addressing the at least one memory cell to be tested in the first bank,

enabling the address decoders and measuring said time delay which characterizes the at least one addressed memory cell,

comparing the measured time delay with a predetermined limit value,

if the measured time delay exceeds the predetermined limit value, designate the address of said at least one memory cell as a weak address, then

continuing with the next address from the step of disabling the address decoders.

13. The method of claim 12 further including the steps of recording the weak address and substituting a redundant group of memory cells for a group of memory cells corresponding to the weak address.