Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware

• US 5,388,215 A
• Filed: 04/28/1994
• Issued: 02/07/1995
• Est. Priority Date: 05/17/1989
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Baker, Ernest D., Joyce, James M., Sanderson, Kenneth R., Grice, Lonnie E., Loffredo, John M., Dinwiddie, John M. Jr.
• Primary Examiner(s): Richardson, Robert L.
• Assistant Examiner(s): Barry, Lance Leonard
• Application Number:
  US08/234,706
• Time in Patent Office: 285 Days
• Field of Search: 395/200, 395/800
• US Class Current: 709/229
• CPC Class Codes: G06F 11/1608 Error detection by comparing the output signals of redundant hardware G06F11/1629, G06F11/1666 take precedence; error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18; checking static stores for correct operation G11C29/00; for logic circuits H03K19/003, H03K19/007; for pulse counters or frequency dividers H03K21/40
• CPC Class Codes: G06F 11/1616 where the redundant component is an I/O device or an adapter therefor
• CPC Class Codes: G06F 11/1625 in communications, e.g. transmission, interfaces
• CPC Class Codes: G06F 11/1633 using mutual exchange of the output between the redundant processing components
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 13/368 with decentralised access control

Abstract

The functions of two virtual operating systems (e. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

Claims

1. A data processing apparatus comprising

first and second data processing systems having respective first and second different architectures and first and second different software operating systems, said first processing system including a first processing unit and system hardware connected thereto and including a main store and a plurality of input/output devices, and said second processing system including a second processing unit,

means connecting said first and second processing systems for transferring information therebetween,

means uncoupling the first processing unit from the system hardware for operating said first processing unit in isolation from said first operating system while receiving information transferred from said second processing system via said connecting means, said information including input/output commands originated by said second processing system,

means in said first processing system for converting said input/output commands originated by said second processing system into modified input/output commands executable by the first processing system, and

means for executing said modified commands in said first processing system.

2. The combination set forth in claim 1 further comprising means for operating said first processing unit in isolation from said first operating system to transfer information from said first processing system to said second processing system via said connecting means.

3. The data processing apparatus of claim 1 wherein the uncoupling means comprises

logic means connected to the first processing unit and responsive to a predetermined virtual address on an address bus of the first processing unit during operation of the first processing unit for blocking an address strobe signal from the first processing unit from being transmitted to said system hardware and for applying said address strobe signal to said connecting means.

4. In a data processing apparatus,

discrete first and second data processing systems having respective first and second different architectures and first and second different software operating systems, said first processing system including a first processing unit, a main store and a plurality of input/output devices operating in conformance with said first architecture, and said second processing system including a second processing unit operating in conformance with said second architecture,

means directly connecting said first and second processing systems to each other for transferring information between said processing systems,

means in said first processing system, including an application program dependent on said first operating system, for selectively operating said first processing unit in isolation from said first operating system while receiving information from said second processing system via said connecting means, said information including input/output commands and data originated by said second processing system in conformance with said second architecture,

means in said first processing system, including said application program, for converting said input/output commands and data originated by said second processing system into modified input/output commands and first data formats conforming to said first architecture, and

means for executing modified commands in said first processing system to cause the transfer of data between said first processing unit and said input/output devices of said first subsystem in said first format.

5. The apparatus of claim 4 further comprising means in said first processing system including said application program for selectively conditioning said first processing unit to operate in isolation to said first operating system to transfer information from said first processing system to said second processing system via said connecting means.

6. A data processing apparatus, comprising:

first and second data processing systems having respective first and second different architectures and first and second different software operating systems, said first and second processing systems including a first and second processing units, first and second main stores and first and second pluralities of input/output devices,

means directly connecting said first and second processing units to each other for transferring information between said processing systems,

means uncoupling each processing unit from its respective main store and input/output devices to operate the uncoupled processing unit in isolation from its respective operating system while sending information to or receiving information from the other processing unit via said connecting means, said information including input/output commands originated by the sending processing unit,

means in each processing system for converting input/output commands received from the other processing system into modified input/output commands executable by the receiving system, and

means for processing said modified commands in said processing system receiving said commands.

7. A method for transferring information between a first processor and a second processor, said second processor being connected to and operating with system hardware including a main storage and a plurality of input/output devices under the control of an operating system, said first processor being alien to the operating system, comprising the steps of:

uncoupling the second processor from said system hardware for isolating the second processor from the operating system,

operatively connecting said first processor and said second processor, and

while said second processor is uncoupled from the system hardware and connected to the first processor, passing information directly between said first processor and said second processor under the control of said second processor and an application program running thereon.

8. A method of transferring data directly between first and second processors, each of which is connected to and operates with respective associated hardware for processing respective program instructions under the control of respective operating systems comprising the steps of:

uncoupling, alternatively, the first or second processor from its respective hardware for isolating said uncoupled processor from its respective operating system,

while said processor is uncoupled, connecting said coupled processor to the other processor and passing data directly between said processors under the control of said uncoupled processor and an application program run thereon.

9. A method of transferring data directly between a pair of processors each of which is connected to and operates with respective associated hardware for processing respective program instructions under the control of respective operating systems comprising the steps of

connecting the processors to each other via a direct path means including a storage means,

selectively uncoupling each of the processors from its respective hardware to isolate the uncoupled processor from its respective operating system,

while each processor is uncoupled, selectively passing data directly between the uncoupled processor and the storage means under the control of said uncoupled processor and a respective application program running thereon.

10. In a data processing system,

a processor and associated hardware for processing information under control of an operating system, said operating system having routines for handling interrupt requests from said processing system on plural priority levels,

data handling apparatus alien to the operating system and including means for initiating additional interrupt requests to the processor on one of said priority levels for data transfer with the processor, said routines being unable to service the interrupt requests from said apparatus;

an application program in the processing system including an additional interrupt handler routine to service the interrupt requests from said apparatus;

means effective upon the initiation of an interrupt request from said apparatus for directing the processor to the additional interrupt handler routine without rejection by said operating system, said system thereafter executing said additional interrupt handler routine on said processor;

means including said application program running on said processor unit selectively uncoupling the processor unit from said hardware to isolate the processor unit from the operating system and coupling the processor unit to said apparatus for transferring data with said apparatus without rejection by the operating system; and

means controlled by the application program notifying the alien apparatus when the data transfer initiated by the interrupt request is complete.

11. A method for transferring information between a first processor and a second processor, said second processor connected to and operating with system hardware including a main storage and a plurality of input/output devices for processing information under the control of an operating system, comprising the steps of:

initiating an interrupt request from said first processor to said second processor,

servicing the interrupt request by means of an interrupt service routine contained in an application program operating on the second processor,

uncoupling the second processor from said system hardware upon servicing of said interrupt request for isolating the second processor from the operating system,

connecting said first processor to said second processor, and

while said second processor is connected to the first processor and uncoupled from said system hardware, passing information directly between said first processor and said second processor under the control of said second processor and said application program running thereon.

12. A data processing apparatus comprising

first and second data processing systems having respective first and second different architectures and first and second different software operating systems, said first and second processing systems including first and second processing units operating in conformance with said first and second architectures,

means directing connecting said first and second processing units to each other for transferring information between said processing systems,

means selectively uncoupling each processing unit from its respective data processing system to operate the uncoupled processing unit in isolation from its respective operating system while sending information to or receiving information from the other processing unit via said connecting means.

13. In a data processing apparatus,

first and second data processing systems having respective first and second different architectures and first and second different software operating systems, said first processing system having a first processing unit and system hardware including a main store and a plurality of input/output devices operating in conformance with said first architecture, and said second processing system including a second processing unit operating in conformance with said second architecture,

means connecting said first and second processing systems for permitting transfer of information between said processing systems,

means uncoupling the first processing unit from the hardware for operating said first processing unit in isolation from said first operating system while receiving information from said second processing system via said connecting means, said information including input/output commands originated by said second processing system,

means in said first processing system for converting said input/output commands originated by said second processing system into modified input/output commands, and

means for executing said modified commands in said first processing system.

14. A method for transferring information between one processor and a second processor, said second processor being connected to and operating with hardware including a main storage and a plurality of input/output devices under the control of an operating system comprising the steps of

uncoupling the second processor from said hardware to operate the second processor in isolation from the operating system and connecting the second processor to said one processor,

while said second processor is isolated from the operating system, passing information directly between said one processor and said second processor under the control of said second processor and an application program running thereon.

15. In a data processing system,

a processing unit and associated hardware for processing information under control of an operating system, said processing unit having an address bus and an address strobe line;

information handling apparatus alien to the operating system;

said processing unit effective during operation thereof for placing on the address bus one of a group of predetermined addresses and for placing an address strobe signal on the address strobe line;

logic means coupled to said address bus and responsive to said one predetermined address for blocking said address strobe signal from being transmitted to said associated hardware and for applying said address strobe signal to the information handling apparatus to operate the processing unit with the information handling apparatus in isolation from said associated hardware and said operating system.

16. The data processing system of claim 15 wherein the operating system has virtual addressing and wherein the group of predetermined addresses are virtual addresses.