Differential latching inverter circuit

• US 5,391,949 A
• Filed: 08/09/1994
• Issued: 02/21/1995
• Est. Priority Date: 05/31/1991
• Status: Expired due to Term

• Current Assignee: Technology Properties Limited LLC
• Original Assignee: Thunderbird Technologies Incorporated
• Inventors: Vinal, deceased, Albert W.
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US08/287,713
• Time in Patent Office: 196 Days
• Field of Search: 307/263, 307/272.1, 307/272.2, 307/279, 307/290, 307/291, 307/350, 307/352, 307/355, 307/530, 307/579, 307/585, 365/189.05, 365/205
• US Class Current: 327/53
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.

Claims

1. A Field Effect Transistor (FET) Differential Latching Inverter (DLI) circuit for sensing signals on first and second bit lines of a memory, comprising:

first and second complementary FET inverters, each of which is connected between first and second reference voltages, and each of which includes a first input, a second input and an output;

each of said first and second complementary inverters producing an inverter transfer function between said first input and said output which is skewed toward one of said first and second reference voltages and which is identical when said first and second inverters turn on and turn off;

the second input of said first inverter being connected to the output of said second inverter, and the second input of said second inverter being connected to the output of said first inverter;

the first bit line being connected to the first input of said first inverter and the second bit line being connected to the first input of said second inverter; and

the outputs of said first and second complementary FET inverters producing output signals for said DLI circuit.

2. The DLI circuit of claim 1 wherein said first and second complementary FET inverters each comprise at least one FET of first conductivity type and at least one FET of second conductivity type;

the product of the square channel saturation current and the ratio of width to length of said at least one FET of said first conductivity type being greater than the product of the square channel saturation current and the ratio of width to length of said at least one FET of said second conductivity type, to thereby produce said skewed inverter transfer function.

3. The DLI circuit of claim 1 wherein the inverter transfer function of said first and second complementary FET inverters is skewed toward one of said first and second reference voltages by a factor of 21/2 less than the midpoint between said first reference voltage and said second reference voltage.

4. The DLI circuit of claim 1 wherein said first reference voltage is five volts, wherein said second reference voltage is ground, and wherein said first and second complementary FET inverters switch logical state at about one volt.

5. The DLI circuit of claim 1 further comprising:

first and second pull-up circuits, each of which includes an input and an output;

the input of said first pull-up circuit being connected to the output of said second complementary FET inverter, and the output of said first pull-up circuit being connected to the output of said first complementary FET inverter; and

the input of said second pull-up circuit being connected to the output of said first complementary inverter, and the output of said second pull-up circuit being connected to the output of said second complementary FET inverter.

6. The DLI of claim 1 further comprising:

first and second pull-up FETs, said first pull-up FET being connected between said first reference voltage and the output of said first complementary FET inverter;

said second pull-up FET being connected between said first reference voltage and the output of said second complementary FET inverter;

the controlling electrode of said first pull-up FET being connected to the output of the second complementary FET inverter; and

the controlling electrode of said second pull-up FET being connected to the output of said first complementary FET inverter.

7. The DLI circuit of claim 1 further comprising first and second pull-up circuits, each of which includes an input and an output;

the output of said first pull-up circuit being connected to the output of said first complementary FET inverter, and the output of said second pull-up circuit being connected to the output of said second complementary inverter;

the inputs of said first and second pull-up circuits being responsive to an input signal to force the outputs of said first and second inverters towards said first reference voltage.

8. The DLI circuit of claim 1 further comprising;

first and second pull-up FETs, the first pull-up FET being connected between the output of said first complementary FET inverter and said first reference voltage, the second pull-up FET being connected between the output of said second complementary FET inverter and said first reference voltage; and

the controlling electrodes of said first and second pull-up FETs being responsive to an input signal to force the outputs of said first and second inverters towards said first reference voltage.

9. The DLI circuit of claim 1 further comprising:

third and fourth complementary FET inverters, each of which is connected between said first and second reference voltages and each of which includes an input and an output;

the output of said first complementary FET inverter being connected to the input of said third complementary FET inverter and the output of said second complementary FET inverter being connected to the input of said fourth complementary FET inverter, the outputs of said third and fourth complementary FET inverters producing buffered output signals for said DLI circuit;

the FETs of each of said third and fourth inverters producing an inverter voltage transfer function which is symmetrical between said first and second reference voltages.

10. The DLI circuit of claim 9 wherein said third and fourth complementary FET inverters each comprise at least one FET of first conductivity type and at least one FET of second conductivity type;

the product of the square channel saturation current and the ratio of width to length of said at least one FET of said first conductivity type being equal to the product of the square channel saturation current and the ratio of width to length of said at least one FET of said second conductivity type, to thereby produce said symmetrical inverter transfer function.

11. The DLI circuit of claim 9:

wherein said third complementary FET inverter comprises a first FET of first conductivity type and a second FET of second conductivity type, which are serially connected between said first and said second reference voltages, with the controlling electrodes of said first and second FETs being said input of said third complementary inverter, and with the connection between the controlled electrodes of said first and second FETs being the output of said third complementary inverter; and

wherein said fourth complementary FET inverter comprises a third FET of first conductivity type and a fourth FET of second conductivity type, which are serially connected between said first and second reference voltages, with the controlling electrodes of said third and fourth FETs being said input of said fourth complementary FET inverter, and with the connection between the controlled electrodes of said third and fourth FETs being the output of said fourth complementary inverter.