Addressing technique for a fault tolerant block-structured storage device

• US 5,392,288 A
• Filed: 02/08/1991
• Issued: 02/21/1995
• Est. Priority Date: 02/08/1991
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Quantum Corporation (Chi Ko Investment Co., Ltd.)
• Inventors: Rudman, Richard A., Kemp, Paul W., Smelser, Donald W.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Decady, Albert
• Application Number:
  US07/652,870
• Time in Patent Office: 1,474 Days
• Field of Search: 371/2.2, 371/40.1, 371/10.1, 371/40.2, 371/40.4
• US Class Current: 714/702
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A fault tolerant addressing arrangement for a solid-state disk comprising partially defective memory devices is provided. The addressing technique increments both row and column addresses when establishing locations for the storage of symbols so that the same rows and columns are not addressed for any two symbols. The technique also complements certain portions of the symbols'"'"' address to ensure addressing of different locations within each memory device.

Claims

1. A method for storing error correction code symbols in a storage array having a plurality of banks of partially defective memory devices coupled to an error correction code unit, said symbols corresponding to a block of information encoded by said error correction code unit to a code block, said method comprising the steps of:

apportioning said error correction code symbols into a plurality of defined groups of symbols;

converting a first of said defined groups of symbols to a plurality of sets of multiple-bit words;

storing each bit of a first word within a first set of words in each memory device of a first bank at a location defined by a bank count, a row address and a column address; and

successively incrementing said column address and storing subsequent to each incremented interval each bit of successive words within said first set in each memory device of said first bank at a location defined by said row address and said successively incremented column address until all of said words within said first set are stored in said array.

2. The method of claim 1 further comprising the step of selectively inverting a predetermined number of most significant bits of said row and column addresses, said predetermined number of bits corresponding to internally partitioned sections of said memory devices.

3. The method of claim 2 wherein the steps of storing further comprises storing each bit of said multiple-bit words in said sections of said memory devices in accordance with said selectively inverted bits such that each bit of said word is stored in a different section of said memory devices.

4. The method of claim 3 further comprising the step of incrementing said bank count, said row address and said column address, and storing each bit of a first word within a second set of words in each memory device of a second bank.

5. The method of claim 4 further comprising the step of successively incrementing said column address and storing subsequent to each incremented interval each bit of successive words within said second set in each memory device of said second bank at a location defined by said incremented bank count and row address, and said successively incremented column address, until all of said words within said second set are stored in said array.

6. The method of claim 5 further comprising the step of incrementing said bank count, said row address and said column address, and storing each bit of a first word within a third set of words in each memory device of a third bank.

7. The method of claim 6 further comprising the step of successively incrementing said column address and storing subsequent to each incremented interval each bit of successive words within said third set in each memory device of said third bank at a location defined by said incremented bank count and row address, and said successively incremented column address, until all of said words within said third set are stored in said array.

8. Apparatus for storing error correction code symbols in a storage array having a plurality of banks of partially defective memory devices coupled to an error correction code unit, said symbols corresponding to a block of information encoded by said error correction code unit to a code block, said apparatus comprising:

means for apportioning said error correction code symbols into a plurality of defined groups of symbols;

means, coupled to said apportioning means, for converting a first of said defined groups of symbols to a plurality of sets of multiple-bit words;

means, coupled to said converting means, for storing each bit of a first word within a first set of words in each memory device of a first bank at a location defined by a bank count, a row address and a column address; and

means, coupled to said storing means, for successively incrementing said column address and means for storing subsequent to each incremented interval each bit of successive words within said first set in each memory device of said first bank at a location defined by said row address and said successively incremented column address until all of said words within said first set are stored in said array.

9. The apparatus of claim 8 further comprising means, coupled to said successively incrementing means, for selectively inverting a predetermined number of most significant bits of said row and column addresses, said predetermined number of bits corresponding to internally partitioned sections of said memory devices.

10. The apparatus of claim 9 wherein said means for storing further comprises means for storing each bit of said multiple-bit words in said sections of said memory devices in accordance with said selectively inverted bits such that each bit of said word is stored in a different section of said memory devices.

11. The apparatus of claim 10 wherein said successively incrementing means further comprises means for incrementing said bank count, said row address and said column address, and means for storing each bit of a first word within a second set of words in each memory device of a second bank.

12. The apparatus of claim 11 wherein said successively incrementing means further comprises means for successively incrementing said column address and means for storing subsequent to each incremented interval each bit of successive words within said second set in each memory device of said first bank at a location defined by said incremented bank count and row address, and said successively incremented column address, until all of said words within said second set are stored in said array.