Layout design to eliminate process antenna effect

  • US 5,393,701 A
  • Filed: 04/08/1993
  • Issued: 02/28/1995
  • Est. Priority Date: 04/08/1993
  • Status: Expired due to Term
First Claim
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1. A method of forming a multi-level conductive interconnection for an integrated circuit on a silicon substrate, wherein there are contact pad areas at the periphery of said interconnection, comprising:

  • forming a patterned layer of conductive polysilicon on said substrate to act as a first conductive contact to said integrated circuit;

    forming an insulating layer over said polysilicon layer;

    forming openings to said polysilicon layer through said insulating layer;

    forming a first layer of metal on said insulating layer such that said metal electrically connects to said polysilicon through said openings;

    forming said contact pad areas with said first layer of metal;

    patterning said first layer of metal to form an electrical break in said first metal interconnection, between said contact pad areas and said integrated circuit, wherein said electrical break electrically isolates said contact pad and said integrated circuit to prevent charge build-up during subsequent processing;

    further processing in a plasma environment that would normally produce electrical charge build-up at a gate oxide of said integrated circuit, but wherein said electrical break prevents said normally produced electrical charge build-up;

    forming and patterning a second insulating layer to form openings for vias to said first metal layer;

    forming a second layer of metal over said contact pad areas and over said electrical break such that said second metal electrically connects to said first metal, via direct contact to said first metal at said contact pad areas and through said openings in said second insulating layer to said first metal interconnection, thereby re-connecting said contact pad areas and said integrated circuit; and

    forming a passivation layer over said second metal layer.

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