Static random access memory cell utilizing a gated diode load element
First Claim
1. In an integrated circuit, a memory cell comprising:
- a word line;
a bit line;
an inverted bit line;
a ground line;
a power line;
a first transistor having a first end coupled to the inverted bit line, a second end, and a gate coupled to the word line;
a second transistor having a first end, a second end coupled to the bit line, and a gate coupled to the word line;
a third transistor having a first end coupled to the second end of the first transistor, a second end coupled to the ground line, and a gate coupled to the first end of the second transistor;
a fourth transistor having a first end coupled to the first end of the second transistor, a second end coupled to the ground line, and a gate coupled to the second end of the first transistor;
a first diode comprising a first end coupled to the power line, and a second end coupled to the second end of the first transistor; and
,a second diode comprising a first end coupled to the power line, and a second end coupled to the first end of the second transistor.
1 Assignment
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Accused Products
Abstract
A memory cell includes gated diodes as load elements. For example, the memory cell includes a word line, a bit line, an inverted bit line, a ground line, a power line, a first transistor, a second transistor, a third transistor, a fourth transistor, a first gated diode and a second gated diode. The first transistor has a first end connected to the inverted bit line, a second end, and a gate connected to the word line. The second transistor has a first end, a second end connected to the bit line, and a gate connected to the word line. The third transistor has a first end connected to the second end of the first transistor, a second end connected to the ground line, and a gate connected to the first end of the second transistor. The fourth transistor has a first end connected to the first end of the second transistor, a second end connected to the ground line, and a gate connected to the second end of the first transistor. The first gated diode includes a first end connected to the power line and a second end connected to the second end of the first transistor. The second gated diode includes a first end connected to the power line and a second end connected to the first end of the second transistor.
50 Citations
16 Claims
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1. In an integrated circuit, a memory cell comprising:
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a word line; a bit line; an inverted bit line; a ground line; a power line; a first transistor having a first end coupled to the inverted bit line, a second end, and a gate coupled to the word line; a second transistor having a first end, a second end coupled to the bit line, and a gate coupled to the word line; a third transistor having a first end coupled to the second end of the first transistor, a second end coupled to the ground line, and a gate coupled to the first end of the second transistor; a fourth transistor having a first end coupled to the first end of the second transistor, a second end coupled to the ground line, and a gate coupled to the second end of the first transistor; a first diode comprising a first end coupled to the power line, and a second end coupled to the second end of the first transistor; and
,a second diode comprising a first end coupled to the power line, and a second end coupled to the first end of the second transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. In an integrated circuit, a memory cell comprising:
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a first line held continuously at a first voltage; a second line held continuously at a second voltage; a load element including a first gated diode having a first end and a second end, the first end being connected to the first line, and a second gated diode having a first end and a second end, the first end being connected to the first line; and
,selection means, coupled to the second end of the first gated diode and the second end of the second gated diode, for selecting the memory cell; wherein when the second end of the first gated diode is at the first voltage, a gate induced leakage current through the first gated diode holds the second end of the first gated diode at the first voltage, and when the second end of the second gated diode is at the first voltage, a gate induced leakage current through the second gated diode holds the second end of the second gated diode at the first voltage. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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Specification