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Static random access memory cell utilizing a gated diode load element

  • US 5,396,454 A
  • Filed: 09/24/1993
  • Issued: 03/07/1995
  • Est. Priority Date: 09/24/1993
  • Status: Expired due to Fees
First Claim
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1. In an integrated circuit, a memory cell comprising:

  • a word line;

    a bit line;

    an inverted bit line;

    a ground line;

    a power line;

    a first transistor having a first end coupled to the inverted bit line, a second end, and a gate coupled to the word line;

    a second transistor having a first end, a second end coupled to the bit line, and a gate coupled to the word line;

    a third transistor having a first end coupled to the second end of the first transistor, a second end coupled to the ground line, and a gate coupled to the first end of the second transistor;

    a fourth transistor having a first end coupled to the first end of the second transistor, a second end coupled to the ground line, and a gate coupled to the second end of the first transistor;

    a first diode comprising a first end coupled to the power line, and a second end coupled to the second end of the first transistor; and

    ,a second diode comprising a first end coupled to the power line, and a second end coupled to the first end of the second transistor.

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