Computer subsystem reset by address dependent RC discharge
First Claim
1. A computer system having means for selectively resetting a particular subsystem in response to a condition of the particular subsystem, said computer system including,a system bus having a multibit address bus,a plurality of subsystems connected to said bus, each subsystem being addressable by said address bus, wherein each subsystem includes a subsystem address decoder and a subsystem reset circuit for generating a subsystem reset signal, said subsystem reset circuit having a distinct subsystem reset circuit address and being responsive to a first signal from said subsystem address decoder;
- a system master for addressing said subsystems over said address bus,said means for selectively resetting a particular subsystem, comprising;
wherein, in response to a condition of the particular subsystem, said system master places said subsystem reset circuit address on said address bus for selected time intervals said system master operating independently of any response from said subsystem;
wherein said subsystem address decoder decodes said subsystem reset circuit address and generates said first signal containing a plurality of timing intervals;
wherein said subsystem reset circuit generates a reset signal in response to said first signal being applied for a particular number of intervals;
wherein said system master creates a waveform signal at the subsystem reset address and subsystem address decoder in response to the timing intervals created by said system master'"'"'s generation of the address signal;
wherein said subsystem address decoder decodes said subsystem reset address and generates said first signal for a plurality of timing intervals and timing durations independent of a response signal to said system master for each of the plurality of timing intervals and timing durations;
wherein said system master operates independently from any response from the subsystem to validate the address bus transaction for an independent subsystem reset;
wherein said subsystem reset circuit generates a waveform signal of incrementally decreasing or increasing voltage in response to said first signal being applied for a predetermined number of intervals and a predetermined timing interval duration; and
wherein said subsystem reset circuit decodes said waveform signal to cause said subsystem to reset itself in response to said first signal being applied for a predetermined number and predetermined duration of intervals.
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Accused Products
Abstract
In a system wherein a system master (11) communicates with a plurality of subsystems (13, 25, 27, 29), each subsystem (13, 25, 27, 29) is associated with a unique reset address and a reset circuit which recognizes that reset address and generates a reset signal. Each reset circuit includes an address decoder (15) for decoding the reset address to produce a signal which closes a logic gate switch (19). The logic gate switch (19) is repeatedly closed in response to repeated assertions of the address to successively discharge the voltage on a capacitor (C). When the capacitor voltage is discharged to a selected level, a buffer level detector circuit (23) generates the reset signal.
38 Citations
5 Claims
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1. A computer system having means for selectively resetting a particular subsystem in response to a condition of the particular subsystem, said computer system including,
a system bus having a multibit address bus, a plurality of subsystems connected to said bus, each subsystem being addressable by said address bus, wherein each subsystem includes a subsystem address decoder and a subsystem reset circuit for generating a subsystem reset signal, said subsystem reset circuit having a distinct subsystem reset circuit address and being responsive to a first signal from said subsystem address decoder; -
a system master for addressing said subsystems over said address bus, said means for selectively resetting a particular subsystem, comprising; wherein, in response to a condition of the particular subsystem, said system master places said subsystem reset circuit address on said address bus for selected time intervals said system master operating independently of any response from said subsystem; wherein said subsystem address decoder decodes said subsystem reset circuit address and generates said first signal containing a plurality of timing intervals; wherein said subsystem reset circuit generates a reset signal in response to said first signal being applied for a particular number of intervals; wherein said system master creates a waveform signal at the subsystem reset address and subsystem address decoder in response to the timing intervals created by said system master'"'"'s generation of the address signal; wherein said subsystem address decoder decodes said subsystem reset address and generates said first signal for a plurality of timing intervals and timing durations independent of a response signal to said system master for each of the plurality of timing intervals and timing durations; wherein said system master operates independently from any response from the subsystem to validate the address bus transaction for an independent subsystem reset; wherein said subsystem reset circuit generates a waveform signal of incrementally decreasing or increasing voltage in response to said first signal being applied for a predetermined number of intervals and a predetermined timing interval duration; and wherein said subsystem reset circuit decodes said waveform signal to cause said subsystem to reset itself in response to said first signal being applied for a predetermined number and predetermined duration of intervals. - View Dependent Claims (2, 3, 4, 5)
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Specification