Controller for two-switch buck-boost converter

• US 5,402,060 A
• Filed: 05/13/1993
• Issued: 03/28/1995
• Est. Priority Date: 05/13/1993
• Status: Expired due to Term

• Current Assignee: Asahi Kasei Toko Power Device Corp. (Asahi Kasei Corporation)
• Original Assignee: TOKO America Incorporated (Murata Manufacturing Co Limited)
• Inventors: Erisman, Brian P.
• Primary Examiner(s): Stephan, Steven L.
• Assistant Examiner(s): BERHANE, ADOLF D
• Application Number:
  US08/062,309
• Time in Patent Office: 684 Days
• Field of Search: 323/259, 323/344, 323/345, 323/222, 323/271, 323/268, 323/282-284, 323/351, 363/101
• US Class Current: 323/268
• CPC Class Codes: G05F 1/62 using bucking or boosting dc sources
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence

Abstract

A controller for a two-switch buck-boost converter accomplishes one-at-a-time switch control by simultaneously employing an analog error signal to control one drive output and an analog inversion of that error signal, with respect to a voltage that is equal to the voltage excursion limit of a timing ramp signal, to control the other drive output. In a second embodiment of the invention, a controller employs a comparator to compare an analog error signal against a given voltage excursion limit of a timing ramp signal to perform the functions of determining which of two drive outputs is to be enabled to be modulated and of modifying the voltage excursion limits of the timing ramp signal such that the voltage excursion limit compared by the comparator is switched between two different voltage excursion limits.

Claims

1. A controller for use with a two-switch buck-boost converter, the controller comprising:

oscillator means for receiving upper and lower input voltages and for generating a timing ramp signal having excursion voltage limits equal to said upper and lower input voltages;

amplifier means having an inverting input for receiving an error signal and a non-inverting input for receiving a selected one of said upper and lower input voltages, said amplifier means being operative for generating an inverted error signal in response to said error signal and said selected one of said upper and lower input voltages;

first comparator means for comparing said error signal to said timing ramp signal, for generating a first pulse-width-modulated signal as a result of comparing said error signal to said timing ramp signal, and for coupling said first pulse-width-modulated signal to a first switch of said two-switch buck-boost converter; and

second comparator means for comparing said inverted error signal to said timing ramp signal, for generating a second pulse-width-modulated signal, and for coupling said second pulse-width-modulated signal to a second switch of said two-switch buck-boost converter.

3. A controller as in claim 1, further comprising latch means for enabling only one of said first and second switches to be modulated during a full cycle of said timing ramp signal.

5. A controller as in claim 1 wherein:

said timing ramp signal comprises a substantially triangular waveform;

said amplifier means is configured to perform an inversion of substantially unity gain of said inverting input with respect to said non-inverting input;

said error signal comprises an amplified and filtered signal having inverse polarity with respect to an output voltage of said two-switch buck-boost converter;

said non-inverting input of said amplifier receives said upper input voltage;

said first switch comprises a buck switch of said two-switch buck-boost converter;

said second switch comprises a boost switch of said two-switch buck-boost converter;

said first comparator means has a polarity configuration selected to cause said first pulse-width-modulated signal to turn ON said buck switch when a voltage of said error signal is greater than a voltage of said timing ramp signal and to turn OFF said buck switch when the voltage of said error signal is less than the voltage of said timing ramp signal; and

said second comparator means has a polarity configuration selected to cause said first pulse-width-modulated signal to turn ON said boost switch when a voltage of said inverted error signal is less than the voltage of said timing ramp signal and to turn OFF said boost switch when the voltage of said error signal is greater than the voltage of said timing ramp signal,

2. A controller for use with a two-switch buck-boost converter, the controller comprising:

oscillator means for receiving upper, intermediate, and lower input voltages and for generating a timing ramp signal having excursion voltage limits selectable between said intermediate and lower input voltages and said intermediate and upper input voltages;

first comparator means for comparing an error signal to said timing ramp signal and for generating a pulse-width-modulated signal;

second comparator means for comparing said error signal to said intermediate input voltage and for generating a two-state select signal;

means responsive to said select signal for selecting one set of said excursion voltage limits of said timing ramp signal when said select signal is in a first state and for selecting the other set of said excursion voltage limits of said timing ramp signal when said select signal is in a second state; and

logic means for gating said pulse-width-modulated signal and said select signal for applying said pulse-width-modulated signal to a first switch of said two-switch buck-boost converter when said select signal is in said first state and for maintaining said first switch in an ON state when said select signal is in said second state, said logic means being further operative for applying said pulse-width-modulated signal to a second switch of said two-switch buck-boost converter when said select signal is in said second state and for maintaining said second switch in an OFF state when said select signal is in said first state.

4. A controller as in claim 2, further comprising latch means for latching said select signal to prevent a change of state of said select signal except when said timing ramp signal is substantially equal to any of said excursion voltage limits.

6. A controller as in claim 2 wherein:

said timing ramp signal comprises a voltage waveform having a substantially fixed rate of excursion between said selectable voltage limits;

said error signal comprises an amplified and filtered signal having inverse polarity with respect to an output voltage of said two-switch buck-boost converter;

said first state of said select signal results from a comparison by said second comparator when a voltage of said error signal is less than said intermediate input voltage and said second state of said select signal results from a comparison by said second comparator when the voltage of said error signal is greater than said intermediate input voltage;

said means responsive to said select signal selects said intermediate and lower excursion voltage limits when said select signal is in said first state and selects said intermediate and upper excursion voltage limits when said select signal is in said second state;

said logic means is configured to apply said pulse-width-modulated signal to a buck switch of said two-switch buck-boost converter when said select signal is in said first state and to maintain a boost switch of said two-switch buck-boost converter in an OFF state when said select signal is in said first state; and

said logic means is further configured to apply said pulse-width-modulated signal to said boost switch when said select signal is in said second state and to maintain said buck switch in an ON state when said select signal is said second state.

7. A process for controlling buck and boost switches of a two-switch buck-boost converter, the process comprising the steps of:

receiving upper and lower input voltages;

generating a timing ramp signal having upper and lower excursion voltage limits equal to said upper and lower input voltages, respectively;

generating a first pulse-width-modulated signal by comparing an error signal with a selected one of said upper and lower input voltages;

coupling said first pulse-width-modulated signal to a first switch of said two-switch buck-boost converter;

forming an inverted error signal as a function of said error signal and said selected one of said upper and lower input voltages;

generating a second pulse-width-modulated signal by comparing said inverted error signal to said timing ramp signal; and

coupling said second pulse-width-modulated signal to a second switch of said two-switch buck-boost converter.

8. A process for controlling buck and boost switches of a two-switch buck-boost converter, the process comprising the steps of:

receiving upper, intermediate, and lower input voltages;

generating a timing ramp signal having excursion voltage limits selectable between the combination of said-intermediate and lower input voltages and the combination of said intermediate and upper input voltages;

generating a pulse-width-modulated signal by comparing an error signal to said timing ramp signal;

generating a two-state select signal by comparing said error signal to said intermediate input voltage;

selecting one combination of said excursion voltage limits of said timing ramp signal when said select signal is in a first state;

selecting the other combination of said excursion voltage limits of said timing ramp signal when said select signal is in a second state; and

applying said pulse-width-modulated signal to a first switch of said two-switch buck-boost converter when said select signal is in said first state;

maintaining said first switch in an ON state when said select signal is in said second state;

applying said pulse-width-modulated signal to a second switch of said two-switch buck-boost converter when said select signal is in said second state; and

maintaining said second switch in an OFF state when said select signal is in said first state,