Adaptive analog minimum/maximum selector and subtractor circuit
First Claim
1. A multi-channel minimum selector and subtractor circuit, including:
- a plurality of input nodes;
a plurality of output nodes;
a plurality of current sourcesa common conductive line;
a plurality of P-Channel MOS transistors, each of said P-Channel MOS transistors having a gate connected to a different one of said input nodes, a source connected to a different one of said current sources, and a drain connected to a fixed voltage source at a potential more negative than the potential at said source of said P-Channel MOS transistor;
a plurality of first switches, each of said first switches connected between said common conductive line and the source of one of a different one of said P-Channel transistors;
a plurality of transconductance amplifiers, each of said transconductance amplifiers having an output connected to a different one of said output nodes, an inverting input, and a non-inverting input connected to the source of a different one of said P-Channel MOS transistors;
a plurality of capacitors, each of said capacitors connected between a fixed voltage source and the inverting input of a different one of said transconductance amplifiers;
a plurality of second switches, each of said second switches connected between the output and the inverting input of a different one of said transconductance amplifiers; and
means for closing all of said first and second switches during a first operating phase of said minimum selector and subtractor circuit, and for opening all of said first and second switches during a second operating phase of said minimum selector and subtractor circuit.
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Abstract
A circuit for use as a channel of a minimum selector and subtractor circuit includes a P-Channel MOS transistor having a gate connected to an input node, a source connected to the output of a current source, and a drain connected to a fixed voltage source. The source of the P-Channel transistor is connectable to a common conductive line through a first switch. The source of the P-Channel transistor is also connected to the non-inverting input of a transconductance amplifier. The inverting input of the transconductance amplifier is connected to a first plate of a capacitor. The second plate of the capacitor is connected to a fixed voltage source such as ground. The output of the transconductance amplifier is connectable to its inverting input through a second switch. The output of the transconductance amplifier forms the output of the minimum selector and subtractor circuit. A plurality of individual channel circuits may all be connected to the common conductive line. The input nodes of the individual channel circuits are each individually connected to a different one of a plurality of analog input lines. The minimum selector and subtractor circuit determines the minimum analog value appearing on the plurality of lines and subtracts that value from the input values on all of the input lines. A maximum selector and subtractor circuit is formed by reversing transistor types.
134 Citations
4 Claims
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1. A multi-channel minimum selector and subtractor circuit, including:
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a plurality of input nodes; a plurality of output nodes; a plurality of current sources a common conductive line; a plurality of P-Channel MOS transistors, each of said P-Channel MOS transistors having a gate connected to a different one of said input nodes, a source connected to a different one of said current sources, and a drain connected to a fixed voltage source at a potential more negative than the potential at said source of said P-Channel MOS transistor; a plurality of first switches, each of said first switches connected between said common conductive line and the source of one of a different one of said P-Channel transistors; a plurality of transconductance amplifiers, each of said transconductance amplifiers having an output connected to a different one of said output nodes, an inverting input, and a non-inverting input connected to the source of a different one of said P-Channel MOS transistors; a plurality of capacitors, each of said capacitors connected between a fixed voltage source and the inverting input of a different one of said transconductance amplifiers; a plurality of second switches, each of said second switches connected between the output and the inverting input of a different one of said transconductance amplifiers; and means for closing all of said first and second switches during a first operating phase of said minimum selector and subtractor circuit, and for opening all of said first and second switches during a second operating phase of said minimum selector and subtractor circuit.
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2. A multi-channel minimum selector and subtractor circuit, including:
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a plurality of input nodes; a plurality of output nodes; a plurality of current sources a common conductive line; a plurality of P-Channel MOS transistors, each of said P-Channel MOS transistors having a gate connected to a different one of said input nodes, a source connected to a different one of said current sources, and a drain; a plurality of N-Channel MOS transistors, each of said P-Channel MOS transistors having a drain connected to the drain of said P-Channel MOS transistor, a source connected to a fixed voltage source and a gate connected to a current limit bias source; a plurality of first switches, each of said first switches connected between said common conductive line and the source of one of a different one of said P-Channel transistors; a plurality of transconductance amplifiers, each of said transconductance amplifiers having an output connected to a different one of said output nodes, an inverting input, and a non-inverting input connected to the source of a different one of said P-Channel MOS transistors; a plurality of capacitors, each of said capacitors connected between a fixed voltage source and the inverting input of a different one of said transconductance amplifiers; a plurality of second switches, each of said second switches connected between the output and the inverting input of a different one of said transconductance amplifiers; and means for opening all of said first and second switches during a first operating phase of said minimum selector and subtractor circuit, and for closing all of said first and second switches during a second operating phase of said minimum selector and subtractor circuit.
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3. A multi-channel maximum selector and subtractor circuit, including:
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a plurality of input nodes; a plurality of output nodes; a plurality of current sinks a common conductive line; a plurality of N-Channel MOS transistors, each of said N-Channel MOS transistors having a gate connected to a different one of said input nodes, a source connected to a different one of said current sinks, and a drain connected to a fixed voltage source at a potential more positive than the potential at said source of said N-Channel MOS transistor; a plurality of first switches, each of said first switches connected between said common conductive line and the source of one of a different one of said N-Channel transistors; a plurality of transconductance amplifiers, each of said transconductance amplifiers having an output connected to a different one of said output nodes, an inverting input, and a non-inverting input connected to the source of a different one of said N-Channel MOS transistors; a plurality of capacitors, each of said capacitors connected between a fixed voltage source and the inverting input of a different one of said transconductance amplifiers; a plurality of second switches, each of said second switches connected between the output and the inverting input of a different one of said transconductance amplifiers; and means for closing all of said first and second switches during a first operating phase of said maximum selector and subtractor circuit, and for opening all of said first and second switches during a second operating phase of said maximum selector and subtractor circuit.
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4. A multi-channel maximum selector and subtractor circuit, including:
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a plurality of input nodes; a plurality of output nodes; a plurality of current sinks; a common conductive line; a plurality of N-Channel MOS transistors, each of said N-Channel MOS transistors having a gate connected to a different one of said input nodes, a source connected to a different one of said current sinks, and a drain; a plurality of P-Channel MOS current-limiting transistors, each of said P-Channel MOS transistors having a drain connected to the drain of said N-Channel MOS transistor, a source connected to a fixed voltage source and a gate connected to a current-limit bias source; a plurality of first switches, each of said first switches connected between said common conductive line and the source of one of a different one of said P-Channel transistors; a plurality of transconductance amplifiers, each of said transconductance amplifiers having an output connected to a different one of said output nodes, an inverting input, and a non-inverting input connected to the source of a different one of said P-Channel MOS transistors; a plurality of capacitors, each of said capacitors connected between a fixed voltage source and the inverting input of a different one of said transconductance amplifiers; a plurality of second switches, each of said second switches connected between the output and the inverting input of a different one of said transconductance amplifiers; and means for closing all of said first and second switches during a first operating phase of said maximum selector and subtractor circuit, and for opening all of said first and second switches during a second operating phase of said maximum selector and subtractor circuit.
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Specification