Image processing system having a sampled filter

• US 5,410,621 A
• Filed: 04/07/1986
• Issued: 04/25/1995
• Est. Priority Date: 12/28/1970
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Couso, Jose L.
• Application Number:
  US06/849,243
• Time in Patent Office: 3,305 Days
• Field of Search: 382/1, 382/43, 382/41, 382/54, 340/720, 358/213.23, 367/100, 364/728.03, 364/521, 364/819, 364/825, 364/827, 364/724, 364/726, 364/720, 364/734
• US Class Current: 382/260
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 13/12 : using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A filter display system is provided to improve display operations. Filtering of display information, such as with correlation filters, improves the image and enhances events of interest. High speed filters for filtering on the fly as the image is being refreshed provides improved capability for iteratively and adaptively enhancing an image. Parallel processing channels provide multiple filtering operations simultaneously for improved performance. Iteratively refreshing a display with filtered information as the filtered image is built up permits operator intervention for optimizing filtering operations.

Claims

1. A display system comprising:

an analog input image circuit generating an analog input image signal;

an analog to digital converter coupled to the analog input image circuit and generating digital input image signal samples in response to the analog input image signal, wherein the analog to digital converter includes a single bit circuit adapted to generate the digital input image signal samples as single bit digital input image signal samples in response to the analog input image signal;

an integrated circuit RAM coupled to the analog to digital converter and storing the single bit digital input image signal samples;

a RAM accessing circuit coupled to the integrated circuit RAM and accessing the single bit digital input image signal samples stored by the integrated circuit RAM;

an integrated circuit read only memory storing multiple bit digital reference signal samples;

a read only memory accessing circuit coupled to the integrated circuit read only memory and accessing the multiple bit digital reference signal samples stored by the integrated circuit read only memory;

a filter processor coupled to the RAM accessing circuit and coupled to the read only memory accessing circuit and generating multiple bit filtered digital image signal samples by filter processing the single bit digital input image signal samples accessed by the RAM accessing circuit in response to the multiple bit digital reference signal samples accessed by the read only memory accessing circuit;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the multiple bit filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered image in response to the analog output filtered image signal.

2. A display system comprising:

an analog input image circuit generating an analog input image signal;

an analog to digital converter coupled to the analog input image circuit and generating digital input image signal samples in response to the analog input image signal, wherein the analog to digital converter includes a multiple bit circuit adapted to generate the digital input image signal samples as multiple bit digital input image signal samples in response to the analog input image signal;

an integrated circuit RAM coupled to the analog to digital converter and storing the multiple bit digital input image signal samples;

a RAM accessing circuit coupled to the integrated circuit RAM and accessing the multiple bit digital input image signal samples stored by the integrated circuit RAM;

an integrated circuit read only memory storing single bit digital reference signal samples;

a read only memory accessing circuit coupled to the integrated circuit read only memory and accessing the single bit digital reference signal samples stored by the integrated circuit read only memory;

a filter processor coupled to the RAM accessing circuit and coupled to the read only memory accessing circuit and generating multiple bit filtered digital image signal samples by filter processing the multiple bit digital input image signal samples accessed by the RAM accessing circuit in response to the single bit digital reference signal samples accessed by the read only memory accessing circuit;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the multiple bit filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered image in response to the analog output filtered image signal.

3. A display system comprising:

an analog input image circuit generating an analog input image signal;

an analog to digital converter coupled to the analog input image circuit and generating digital input image signal samples in response to the analog input image signal, wherein the analog to digital converter includes a single bit circuit adapted to generate the digital input image signal samples as single bit digital input image signal samples in response to the analog input image signal;

an integrated circuit RAM coupled to the analog to digital converter and storing the single bit digital input image signal samples;

a RAM accessing circuit coupled to the integrated circuit RAM and accessing the single bit digital input image signal samples stored by the integrated circuit RAM;

an integrated circuit read only memory storing single bit digital reference signal samples;

a read only memory accessing circuit coupled to the integrated circuit read only memory and accessing the single bit digital reference signal samples stored by the integrated circuit read only memory;

a filter processor coupled to the RAM accessing circuit and coupled to the read only memory accessing circuit and generating multiple bit filtered digital image signal samples by filter processing the single bit digital input image signal samples accessed by the RAM accessing circuit in response to the single bit digital reference signal samples accessed by the read only memory accessing circuit;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the multiple bit filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered image in response to the analog output filtered image signal.

4. A display system comprising:

an analog input image circuit generating an analog input image signal;

an analog to digital converter having a multiple bit circuit coupled to the analog input image circuit and generating multiple bit digital input image signal samples in response to the analog input image signal;

an integrated circuit RAM coupled to the analog to digital converter and storing the multiple bit digital input image signal samples;

a RAM accessing circuit coupled to the integrated circuit RAM and accessing the multiple bit digital input image signal samples stored by the integrated circuit RAM;

an integrated circuit read only memory storing multiple bit digital reference signal samples;

a read only memory accessing circuit coupled to the integrated circuit read only memory and accessing the multiple bit digital reference signal samples stored by the integrated circuit read only memory;

a filter processor coupled to the RAM accessing circuit and coupled to the read only memory accessing circuit and generating multiple bit filtered digital image signal samples by filter processing the multiple bit digital input image signal samples accessed by the RAM accessing circuit in response to the multiple bit digital reference signal samples accessed by the read only memory accessing circuit;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the multiple bit filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered image in response to the analog output filtered image signal.

5. A display system comprising:

an analog input image circuit generating an analog input image signal;

an analog to digital converter coupled to the analog input image circuit and generating digital input image signal samples in response to the analog input image signal, wherein the analog to digital converter includes a multiple bit circuit adapted to generate the digital input image signal samples as multiple bit digital input image signal samples in response to the analog input image signal;

an integrated circuit RAM coupled to the analog to digital converter and storing the multiple bit digital input image signal samples;

a RAM accessing circuit coupled to the integrated circuit RAM and accessing the multiple bit digital input image signal samples stored by the integrated circuit RAM;

an integrated circuit read only memory storing multiple bit digital reference signal samples;

a read only memory accessing circuit coupled to the integrated circuit read only memory and accessing the multiple bit digital reference signal samples stored by the integrated circuit read only memory;

a filter processor coupled to the RAM accessing circuit and coupled to the read only memory accessing circuit and generating multiple bit filtered digital image signal samples having a multiple bit digital resolution with more bits than the multiple bit digital input image signal samples and more bits than the multiple bit digital reference signal samples by filter processing the multiple bit digital input image signal samples accessed by the RAM accessing circuit in response to the multiple bit digital reference signal samples accessed by the read only memory accessing circuit;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the multiple bit filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered image in response to the analog output filtered image signal.

6. A display system comprising:

an analog input image circuit having a transducer generating a transducer signal and a signal processing circuit coupled to the transducer and generating an analog input image signal in response to the transducer signal;

an analog to digital converter coupled to the analog input image circuit and generating digital input image signal samples in response to the analog input image signal;

an integrated circuit RAM coupled to the analog to digital converter and storing the digital input image signal samples;

a RAM accessing circuit coupled to the integrated circuit RAM and accessing the digital input image signal samples stored by the integrated circuit RAM;

an integrated circuit read only memory storing digital transducer reference signal samples;

a read only memory accessing circuit coupled to the integrated circuit read only memory and accessing the digital transducer reference signal samples stored by the integrated circuit read only memory;

a filter processor coupled to the RAM accessing circuit and coupled to the read only memory accessing circuit and generating filtered digital transducer image signal samples by filter processing the digital input image signal samples accessed by the RAM accessing circuit in response to the digital transducer reference signal samples accessed by the read only memory accessing circuit;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the filtered digital transducer image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered transducer image in response to the analog output filtered image signal.

7. A display system comprising:

an analog input image circuit having a plurality of analog input circuit channels, each one of the plurality of channels generating an analog input image signal;

an analog to digital converter coupled to the analog input image circuit and generating a plurality of channels of digital input image signal samples in response to the plurality of channels of analog input image signal;

an integrated circuit RAM coupled to the analog to digital converter and storing the plurality of channels of digital input image signal samples;

a RAM accessing circuit coupled to the integrated circuit RAM and accessing a plurality of channels of digital input image signal samples stored by the integrated circuit RAM;

an integrated circuit read only memory storing a plurality of channels of digital reference signal samples;

a read only memory accessing circuit coupled to the integrated circuit read only memory and accessing the plurality of channels of digital reference signal samples stored by the integrated circuit read only memory;

a plurality of channels of filter processors, each channel coupled to the RAM accessing circuit and coupled to the read only memory accessing circuit and generating filtered digital image signal samples by filter processing the digital input image signal samples accessed by the related channel of RAM accessing circuit in response to the digital reference signal samples accessed by the related channel of the read only memory accessing circuit;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the plurality of channels of filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying the plurality of channels of filtered images in response to the analog output filtered image signal.

8. A display system comprising:

a synchronization circuit generating a synchronization signal;

an analog input image circuit generating an analog input image signal;

an analog to digital converter coupled to the analog input image circuit and generating digital input image signal samples in response to the analog input image signal;

an integrated circuit RAM coupled to the analog to digital converter and storing the digital input image signal samples;

a RAM accessing circuit coupled to the integrated circuit RAM and accessing the digital input image signal samples stored by the integrated circuit RAM;

an integrated circuit read only memory storing digital reference signal samples and storing instructions;

a read only memory accessing circuit coupled to the integrated circuit read only memory and accessing the digital reference signal samples and the stored instructions stored by the integrated circuit read only memory;

a programmable filter processor coupled to the RAM accessing circuit, to the read only memory accessing circuit, to the read only memory accessing circuit, and to the synchronization circuit and generating filtered digital image signal samples in synchronization with the synchronization signal by filter processing the digital input image signal samples accessed by the RAM accessing circuit in response to the digital reference signal samples accessed by the read only memory accessing circuit, in response to the stored instructions accessed by the read only memory accessing circuit, and in response to the synchronization signal;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the filtered digital image signal samples; and

a display coupled to the digital to analog converter and to the synchronization circuit and displaying a filtered image in response to the analog output filtered image signal and in synchronization with the synchronization signal.

9. A display system comprising:

an analog input image circuit generating an analog input image signal;

an analog to digital converter coupled to the analog input circuit and generating digital input image signal samples in response to the analog input image signal, wherein the analog to digital converter includes a single bit circuit generating the digital input image signal samples as single bit digital input image signal samples in response to the analog input image signal;

an integrated circuit memory coupled to the analog to digital converter and storing the digital input image signal samples;

a filter processor coupled to the integrated circuit memory and generating filtered digital image signal samples by filter processing the digital input image signal samples stored by the integrated circuit memory;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered image in response to the analog output filtered image signal.

10. A display system comprising:

an analog input image circuit generating an analog input image signal;

an analog to digital converter coupled to the analog input circuit and generating single bit digital input image signal samples in response to the analog input image signal;

an integrated circuit memory coupled to the analog to digital converter and storing the single bit digital input image signal samples;

a filter processor coupled to the integrated circuit memory and generating multiple bit filtered digital image signal samples by filter processing the single bit digital input image signal samples stored by the integrated circuit memory;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the multiple bit filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered image in response to the analog output filtered image signal.

11. A display system comprising:

an analog input image circuit generating an analog input image signal;

a reference signal memory storing single bit reference signal samples;

an analog to digital converter coupled to the analog input circuit and generating multiple bit digital input image signal samples in response to the analog input image signal;

an integrated circuit memory coupled to the analog to digital converter and storing the multiple bit digital input image signal samples;

a filter processor coupled to the integrated circuit memory and to the reference signal memory and generating multiple bit filtered digital image signal samples by filter processing the multiple bit digital input image signal samples stored by the integrated circuit memory in response to the single bit reference signal samples;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the multiple bit filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered image in response to the analog output filtered image signal.

12. A display system comprising:

an analog input image circuit generating an analog input image signal;

a reference signal memory storing single bit reference signal samples;

an analog to digital converter coupled to the analog input circuit and generating single bit digital input image signal samples in response to the analog input image signal;

an integrated circuit memory coupled to the analog to digital converter and storing the single bit digital input image signal samples;

a filter processor coupled to the integrated circuit memory and coupled to the reference signal memory and generating multiple bit filtered digital image signal samples by filter processing the single bit digital input image signal samples stored by the integrated circuit memory in response to the single bit reference signal samples;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the multiple bit filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered image in response to the analog output filtered image signal.

13. A display system comprising:

an analog input image circuit generating an analog input image signal;

a reference signal memory storing multiple bit reference signal samples;

an analog to digital converter coupled to the analog input image circuit and generating multiple bit digital input image signal samples in response to the analog input image signal;

an integrated circuit memory coupled to the analog to digital converter and storing the multiple bit digital input image signal samples;

a filter processor coupled to the reference signal memory and to the integrated circuit memory and generating multiple bit filtered digital image signal samples by filter processing the multiple bit digital input image signal samples stored by the integrated circuit memory in response to the multiple bit reference signal samples;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the multiple bit filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered image in response to the analog output filtered image signal.

14. A display system comprising:

an analog input image circuit generating an analog input image signal;

an analog to digital converter coupled to the analog input circuit and generating multiple bit digital input image signal samples in response to the analog input image signal;

an integrated circuit memory coupled to the analog to digital converter and storing the multiple bit digital input image signal samples;

a filter processor coupled to the integrated circuit memory and generating multiple bit filtered digital image signal samples having more resolution than the digital input image signal samples by filter processing the multiple bit digital input image signal samples stored by the integrated circuit memory;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the multiple bit filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered image in response to the analog output filtered image signal.

15. A display system comprising:

an analog input image circuit having a transducer generating a transducer signal and a signal processing circuit coupled to the transducer and generating an analog input image signal in response to the transducer signal;

an analog to digital converter coupled to the analog input circuit and generating digital input image signal samples in response to the analog input image signal;

an integrated circuit memory coupled to the analog to digital converter and storing the digital input image signal samples;

a filter processor coupled to the integrated circuit memory and generating filtered digital transducer image signal samples by filter processing the digital input image signal samples shared by the integrated circuit memory;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the filtered digital transducer image signal samples; and

a display coupled to the digital to analog converter and displaying a filtered transducer image in response to the analog output filtered image signal.

16. A display system comprising:

an analog input image circuit having a plurality of channels of the analog input circuit, each one of the plurality of channels generating an analog input image signal;

an analog to digital converter coupled to the analog input circuit and generating a plurality of channels of digital input image signal samples in response to the plurality of channels of analog input image signals;

an integrated circuit memory coupled to the analog to digital converter and storing the plurality of channels of digital input image signal samples;

a plurality of channels of filter processors, each channel coupled to the integrated circuit memory and generating filtered digital image signal samples by filter processing the related channel of the digital input image signal samples stored by the integrated circuit memory;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the plurality of channels of filtered digital image signal samples; and

a display coupled to the digital to analog converter and displaying the plurality of channels of filtered images in response to the analog output filtered image signal.

17. A display system comprising:

a synchronization circuit generating a synchronization signal;

an analog input image circuit generating an analog input image signal;

an analog to digital converter coupled to the analog input circuit and generating digital input image signal samples in response to the analog input image signal;

an integrated circuit memory coupled to the analog to digital converter and storing the digital input image signal samples;

an integrated circuit read only memory storing instructions;

a read only memory accessing circuit coupled to the integrated circuit read only memory and accessing the stored instructions;

a programmable filter processor coupled to the read only memory accessing circuit, to the integrated circuit memory, and to the synchronization circuit and generating the filtered digital image signal samples in synchronization with the synchronization signal by filter processing the digital input image signal samples stored by the integrated circuit memory in response to the stored instructions accessed by the read only memory accessing circuit and in response to the synchronization signal;

a digital to analog converter coupled to the filter processor and generating an analog output filtered image signal in response to the filtered digital image signal samples; and

a display coupled to the digital to analog converter and to the synchronization circuit and displaying a filtered image in response to the analog output filtered image signal and in synchronization with the synchronization signal.