Integrated power switch structure having a vertical thyristor controlled by a lateral MOS transistor

• US 5,413,313 A
• Filed: 07/08/1993
• Issued: 05/09/1995
• Est. Priority Date: 01/09/1991
• Status: Expired due to Fees

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Mutterlein, Bernward, Vogt, Holger
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/087,799
• Time in Patent Office: 670 Days
• Field of Search: 257/133, 257/67, 257/70, 257/109, 257/137, 257/378, 257/379
• US Class Current: 257/137
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect

Abstract

An integrated power switch structure comprises a lateral MOS transistor (3) and a lateral or vertical thyristor (2). The drain-source path of the lateral MOS transistor (3) is in series with the cathode-anode path of the thyristor (2). In order to ensure that the power switch structure reliably switches on and off with great dielectric strength and low switch-on resistance, at least the source electrode of the lateral MOS transistor (3) is insulated against the substrate (7) by means of a buried oxide layer (8) in accordance with the present invention.

Claims

1. An integrated power switch structure, which comprises a vertical thyristor controlled by a lateral MOS transistor, wherein said thyristor is constructed as a four-layer thyristor comprising an anode layer, a first base layer doped contrary to said anode layer, an additional base layer doped contrary to said first base layer, and a cathode layer, characterized in that

in the main current path of the said power switch structure, said lateral MOS transistor has its drain-source path connected in series with the cathode-anode path of the thyristor,

a buried oxide layer insulates at least a source electrode of the lateral MOS transistor against the substrate, and the first base layer is arranged below said source electrode.

2. An integrated power switch structure according to claim 1, characterized in that said buried oxide layer encloses said lateral MOS transistor in a trough-like manner.

3. An integrated power switch structure according to claim 2, characterized in that said thyristor is provided with a vertical npnp four-layer structure,

said buried oxide layer lies in an additional p-base layer bordering on a n-cathode layer, and

that said lateral MOS transistor is an NMOS transistor whose drain electrode is connected to said cathode of the thyristor and whose source electrode defines together with said anode layer of said thyristor the main current path of the power switch structure.

4. An integrated power switch structure according to claim 1, characterized by an additional MOS transistor, positioned on said structure so that when an adequate input voltage is applied to its gate electrode, charge carriers will be injected into said first base layer of an npnp-four-layer structure of the thyristor, said first base layer bordering on said anode layer.

5. An integrated power switch structure according to claim 4, characterized in that said gate electrode of said additional MOS transistor is connected to a gate electrode of said lateral MOS transistor.

6. An integrated power switch structure according to claim 4, characterized in that said additional MOS transistor is an NMOS transistor whose source electrode is connected to a n+-cathode layer of said thyristor and whose drain electrode is defined by said first base layer bordering on said anode layer.

7. An integrated power switch structure according to claim 1, characterized in that a layer doped contrary to said first base layer is provided between said buried oxide layer and said first base layer, and that said layer encloses said buried oxide layer.

8. An integrated power switch structure according to claim 7, characterized in that said layer doped contrary to the said first base layer merges with said additional base layer of said thyristor.

9. An integrated power switch structure according to claim 7, characterized in that a region, which is highly doped contrary to said first base layer, borders on said layer doped contrary to said first base layer and is connected to the source electrode of said lateral MOS transistor.

10. An integrated power switch structure according to claim 2, characterized in that said thyristor is provided with a vertical npnp four-layer structure,

said buried oxide layer lies in said p-doped layer bordering on said additional base layer, and

that said lateral MOS transistor is an NMOS transistor having a drain electrode connected to said cathode of said thyristor and having a source electrode which defines together with said anode layer of said thyristor the main current path of the power switch structure.