Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer

• US 5,416,043 A
• Filed: 07/12/1993
• Issued: 05/16/1995
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Reedy, Ronald E.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/090,400
• Time in Patent Office: 673 Days
• Field of Search: 437/21, 437/25, 437/26, 437/84, 437/62, 437/973, 148/DIG. 150
• US Class Current: 438/479
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H10B 10/15 comprising a resistor load element

Abstract

A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options.

Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented.

Advantages include threshold voltages determined by fundamental material properties; high performance devices due to reduced carrier scattering, low transverse electric fields and elimination of the body effect; threshold voltages virtually independent of temperature; simplicity of modeling due to reduction or elimination of parasitic effects; device and process simplicity; ease of scaling and an option for inherently symmetric threshold voltages for N-channel and P-channel MOSFETs (i.e. |V_tn |=|V_tp |).

Claims

1. A method of fabricating a silicon on sapphire wafer having an intrinsic silicon layer on a sapphire substrate, said method comprising the steps of:

epitaxially depositing a layer of silicon on a surface of a sapphire substrate;

implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;

maintaining said layer of silicon at or below a temperature of approximately zero degrees centigrade (0°

C.) such that said temperature is substantially uniform throughout said layer of silicon during said ion implanting step; and

annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed.

2. A method as defined in claim 1 wherein said implanting step further comprises the step of selecting the energy and intensity of said implanting ions from within a range of energy and intensity values having a lower limit which is sufficient to amorphize said buried region of silicon and an upper limit which is insufficient to release substrate-originated contaminants into said silicon layer.

3. A method as defined in claim 1 further comprising the step of performing a high temperature anneal sequence at or below approximately 950°

C. in a non-oxidizing environment thereby removing residual defects in said layer of silicon without introducing bandgap or interface states.

4. A method as defined in claim 3 wherein said step of performing a high temperature anneal sequence in a non-oxidizing environment to remove residual defects in said layer of silicon without introducing bandgap or interface states further comprises selecting the temperature of said high temperature anneal to be within the range of from approximately 900°

C. to approximately 950°

C.

5. A method as defined in claim 1 further comprising the steps of:

oxidizing a portion of said layer of silicon thereby leaving a thin layer of intrinsic silicon interposed between said sapphire substrate and said oxidized layer; and

etching away said oxidized layer.

6. A method as defined in claim 5 further comprising the step of controlling said steps of oxidizing and etching to reduce said layer of silicon on said sapphire substrate to a thickness which is in the range of from approximately 50 nm to approximately 110 nm.

7. A method as defined in claim 1 wherein said step of annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region further comprises selecting the temperature of said annealing step to be within the range of from approximately 500°

C. to approximately 600°

C.

8. A method as defined in claim 1 wherein said step of implanting a given ion species into said layer of silicon further comprises the steps of:

selecting silicon as said given ion species; and

selecting the energy and intensity of said silicon ions from within a range of energy and intensity values having a lower limit which is sufficient to amorphize said buried region of silicon and an upper limit which is insufficient to release substrate-originated contaminants into said silicon layer.

9. A method as defined in claim 8 wherein said step of selecting said silicon ion energy further comprises selecting said silicon ion energy to be within the range of from approximately 185 keV to approximately 200 keV.

10. A method as defined in claim 8 wherein said step of selecting said silicon ion intensity further comprises selecting said silicon ion intensity to be within the range of from approximately 5×

10¹⁴ cm^-2 to approximately 7×

10¹⁴ cm^-2.

11. A method as defined in claim 1 wherein said step of maintaining said layer of silicon at or below a temperature of approximately zero degrees centigrade (0°

C.) which is substantially uniform throughout said layer of silicon during said ion implanting step further comprises flooding a surface of said sapphire substrate which does not have said layer of silicon deposited thereon with a cooled gas.

12. A method as defined in claim 1 wherein said step of epitaxially depositing a layer of silicon on a surface of a sapphire substrate further comprising controlling the deposition to produce a silicon layer having a thickness in the range of from approximately 250 nm to approximately 270 nm.

13. A method of fabricating a silicon on sapphire wafer having an intrinsic silicon layer on a sapphire substrate, said method comprising the steps of:

epitaxially depositing a layer of silicon on a surface of a sapphire substrate;

positioning said sapphire substrate adjacent a chamber through which flows a coolant such that said coolant contacts said sapphire substrate;

implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;

controlling the flow rate or the temperature or both the flow rate and the temperature of said coolant through said chamber to maintain said layer of silicon substantially at or below a temperature of approximately zero degree centigrade (0°

) during said ion implanting step; and

annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed.

14. A method as defined in claim 13 further comprising the step of flowing a gaseous coolant through said chamber.

15. A method as defined in claim 14 further comprising the step of selecting nitrogen as said gaseous coolant.