Low distortion CMOS switch system

• US 5,422,588 A
• Filed: 06/14/1993
• Issued: 06/06/1995
• Est. Priority Date: 06/14/1993
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Wynne, John
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): NGUYEN, TIEP HUU
• Application Number:
  US08/076,456
• Time in Patent Office: 722 Days
• Field of Search: 307/571, 307/584, 307/585, 307/243, 307/304, 327/427, 327/434, 327/437, 327/407, 327/408, 327/581
• US Class Current: 327/437
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors

Abstract

A low distortion CMOS switch system includes a plurality of N-channel and a plurality of P-channel transistors with their drain and source terminals connected in parallel for receiving an input signal to be switched; and a control circuit for providing a different positive drive voltage to the gate of each of the N-channel transistors and a different negative drive voltage to the gate of each of the P-channel transistors to produce substantially constant "on" resistance, R_ON, throughout the range of the switched signal conducted through the drain and source terminals, and for providing the same negative drive voltage to the gate of each of the N channel transistors and the same positive drive voltage to the gate of each of the P channel transistors to turn off the transistors.

Claims

1. A load distortion CMOS switch system comprising:

a plurality of N-channel and a plurality of P-channel transistors, each having a gate, a source and a drain, with their drain and source terminals connected in parallel for receiving an input signal varying over a predetermined range to be switched; and

a control circuit for providing a different positive drive voltage to the gate of each of said N-channel transistors and a different negative drive voltage to the gate of each of said P-channel transistors to produce a substantially uniform on resistance, R_ON, throughout the range of the switched signal conducted through the drain and source terminals and for providing substantially identical negative drive voltages to the gates of each of said N-channel transistors and substantially identical positive drive voltages to the gates of each of said P-channel transistors to turn off said transistors.

2. The low distortion CMOS switch system of claim 1 in which said control circuit includes a voltage divider circuit for providing said different positive and negative voltages for each of said gates of said transistors.

3. The low distortion CMOS switch system of claim 2 in which said control circuit includes a switching means for applying positive and negative voltages to said gates of said transistors to turn on said transistors and for applying said substantially identical positive and negative voltages to said gates of said transistors to turn off said transistors.

4. A low distortion semiconductor switch system comprising:

a plurality of N-channel and a plurality of P-channel semiconductors, each semiconductor having a gate, a source, and a drain, with their load terminals connected in parallel for receiving an input signal, varying over a predetermined range, to be switched; and

a control circuit for providing a different drive voltage to the gate of each of said P-channel and to the gate of each of said N-channel semiconductors to produce a substantially uniform "on" resistance, R_ON, throughout the range of the switched signal conducted through the load terminals.

5. The low distortion semiconductor switch system of claim 4 in which said semiconductor switch system is a CMOS switch and said semiconductors are transistors with their load terminals being drain and source terminals.

6. The low distortion semiconductor switch system of claim 4 in which said control circuit includes a voltage divider circuit for providing different positive and negative voltages for each of said gates of said transistors.

7. The low distortion semiconductor switch system of claim 6 in which said control circuit includes a switching means for applying positive and negative voltages to said gates of transistors to turn on said transistors and for applying said substantially identical positive and negative voltages to said gates of said transistors to turn off said transistors.