Semiconductor memory device

• US 5,422,839 A
• Filed: 09/10/1993
• Issued: 06/06/1995
• Est. Priority Date: 09/10/1992
• Status: Expired due to Term

• Current Assignee: PS4 Luxco S.a.r.l.
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Inventors: Ishibashi, Koichiro, Morita, Sadayuki, Aoto, Toshiro, Sasaki, Katsuro, Komiyaji, Kunihiro
• Primary Examiner(s): Popek, Joseph A.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/118,645
• Time in Patent Office: 634 Days
• Field of Search: 365/51, 365/63, 365/154, 365/155, 365/156, 365/205, 365/206, 365/207, 365/208, 365/230.03, 365/200, 365/201, 257/773, 257/774, 257/775, 257/776, 257/758
• US Class Current: 365/51
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

A semiconductor static memory device, which has an increased storage capacity without imposing an increased access time, includes first, second and third metallic layers. To begin, word lines for the transfer MOSFETS are formed of the same polysilicon layer used to form the gate electrodes of the transfer MOSFETs of the memory device. A metallic layer of the first layer is used for local word lines, with the polysilicon word lines and local word lines being connected at their ends or inside of cell arrays. A metallic layer of the second layer is used for bit layers, and a metallic layer of the third layer is used for main word lines. Consequently, the word lines have a decreased time constant, allowing fast memory access. Each of sense amplifiers used in the memory device are formed with MOSFETs, which are disposed divisionally in adjacent locations. Preferably the gate electrodes of the divided MOSFETs are located symmetrically. In this case, the offset voltage of the sense amplifiers decreases significantly.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cells of static type formed on a semiconductor substrate in a row direction and a column direction to form a memory cell array, each memory cell including two drive MOSFETs, two transfer MOSFETs and two load elements;

a first metallic layer formed over at least said load elements;

a second metallic layer formed over said metallic layer of the first layer wherein said second metallic layer has a lower sheet resistance than said first metallic layer; and

a third metallic layer formed over said metallic layer of the second layer, wherein said third metallic layer has a lower sheet resistance than said second metallic layer,

wherein first word lines coupled to gate electrodes of the transfer MOSFETs of memory cells arrayed in the row direction are formed of a polysilicon layer,

wherein a bit line pair connected to the transfer MOSFETs of memory cells arrayed in the column direction is formed in the column direction by said second metallic layer,

wherein main word lines, which are disposed over said memory cells arrayed in the row direction and selected by row decoders, are formed by said third metallic layer,

wherein local word lines, which are selected by signals on said main word lines, are formed in the row direction by said first metallic layer,

wherein said local word lines and said first word lines are connected to extend in parallel with each other, and

wherein said local word lines have a lower sheet resistance than said first word lines.

2. A semiconductor memory device according to claim 1 further including:

first MOSFETs coupled between said bit lines of said bit line pairs to reduce the voltage differences of bit lines of said bit line pairs when said memory device turns from data writing to data reading.

3. A semiconductor memory device according to claim 2, wherein said first MOSFETs are located substantially at a mid-point of said bit lines.

4. A semiconductor memory device according to claim 1 further including:

MOSFETs which are connected across bit line pairs and adapted to become conductive during data reading;

column selection means for conducting signals on bit line pairs selected by column decoders to common data line pairs; and

amplifiers for amplifying the data signals placed on said common data line pairs,

wherein each of said amplifiers includes MOSFETs each of which is formed divisionally in adjacent locations on said substrate, wherein the divided MOSFETs have their gate electrodes located axial symmetrically or point symmetrically.

5. A semiconductor memory device according to claim 1, wherein said memory cell array is divided in said row direction into a plurality of cell arrays.

6. A semiconductor memory device according to claim 5, wherein said memory cells are further divided into a plurality of blocks smaller in number than said cell arrays, each block being connected to data bus pairs for delivering signals on common data line pairs after the signals have been amplified by amplifiers, and

wherein in a normal operation mode, one of said blocks is selected and data are read out of memory cells in the selected block, and in a test mode, said blocks are selected, data are read out of memory cells in the blocks, amplified and placed on the data buses, and the data on the data bus pairs undergo a logical operation, wherein a result of said logical operation is outputted.

7. A semiconductor memory device according to claim 5, wherein said memory cells are further divided into a plurality of blocks smaller in number than said cell arrays, and

wherein each of said blocks is provided with relief memory cells used to relieve defective memory cells, a defective memory cell in a block being relieved by a relief memory cell within the same block.

8. A semiconductor memory device according to claim 1, wherein said gate electrodes of said transfer transistors are formed of the same polysilicon layer as the first word lines.

9. A semiconductor memory device according to claim 1, wherein said main word lines are longer than said local word lines.

10. A semiconductor memory device according to claim 1, wherein said first metallic layer is comprised of tungsten, and said second and third metallic layers are comprised of aluminum.

11. A semiconductor memory device according to claim 10, wherein said third metallic layer is thicker than said first and second metallic layers.

12. A semiconductor memory device according to claim 10, wherein said first metallic layer has a sheet resistance of approximately 500 Ω

/sq, said second metallic layer has a sheet resistance of approximately 200 Ω

/sq, and the third metallic layer has a sheet resistance of approximately 50 Ω

/sq.

13. A semiconductor memory device comprising:

a plurality of memory cells of static type formed on a semiconductor substrate in a row direction and a column direction to form a memory cell array, each memory cell including two drive MOSFETs, two transfer MOSFETs and two load elements;

first word lines formed of polysilicon coupled to gate electrodes of said transfer transistors of said memory cells, wherein said first word lines each have first and second ends and extend in said row direction;

local word lines formed of a first metallic layer, wherein said local word lines are coupled to the first and second ends of the first word lines and extend substantially in parallel with said first word lines in the row direction, and wherein said local word lines have a lower sheet resistance than said first word lines;

bit line pairs, formed of a second metallic layer, extending in said column direction to be coupled to source-drain paths of said transfer transistors, wherein said second metallic layer is formed over said first metallic layer and has a lower sheet resistance than said first metallic layer; and

main word lines, formed of a third metallic layer, extending in said row direction and coupled to said local word lines, wherein said main word lines are longer than said local word lines and said first word lines, and wherein said third metallic layer is formed over said second metallic layer and has a lower sheet resistance than said second metallic layer.

14. A semiconductor memory device according to claim 13, wherein said gate electrodes of said transfer transistors are formed of the same polysilicon layer as the first word lines.

15. A semiconductor memory device according to claim 13, wherein said first metallic layer is comprised of tungsten, and said second and third metallic layers are comprised of aluminum.

16. A semiconductor memory device according to claim 15, wherein said third metallic layer is thicker than said first and second metallic layers.

17. A semiconductor memory device according to claim 15, wherein said first metallic layer has a sheet resistance of approximately 500 Ω

/sq, said second metallic layer has a sheet resistance of approximately 200 Ω

/sq, and the third metallic layer has a sheet resistance of approximately 50 Ω

/sq.

18. A semiconductor memory device according to claim 13, wherein said first metallic layer has a sheet resistance of approximately 500 Ω

/sq, said second metallic layer has a sheet resistance of approximately 200 Ω

/sq, and the third metallic layer has a sheet resistance of approximately 50 Ω

/sq.