Semiconductor memory device

• US 5,424,989 A
• Filed: 08/20/1993
• Issued: 06/13/1995
• Est. Priority Date: 08/21/1992
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sakihama, Kazuhisa, Hagiwara, Norio
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/109,488
• Time in Patent Office: 662 Days
• Field of Search: 365/200, 365/201, 371/10.1, 371/10.2
• US Class Current: 365/201
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells

Abstract

A semiconductor memory device having information data storing cells and error correction data storing memory cells. When information data is inputted, error correction data related to the information data is formed. In a usual use, the information data and the error correction data are stored in the corresponding memory cells. An external test signal, inputted as the information data, can be stored in the error correction data storing memory cells by a write control signal. In a usual use, the information data stored in the information data storing cells are outputted, as they are or corrected if erroneous. The test signal stored in the error correction data storing memory can be outputted by an output control signal.

Claims

1. A semiconductor memory device, comprising:

a memory cell array formed by arranging memory cells composed of information data storing cells and error correction data storing memory cells;

accepting means for accepting information data of a first amount;

error correction data forming means for forming error correction data of a second amount less than the first amount and related to the information data inputted from the accepting means;

writing means for storing data to be written in the information data storing cells and data to be written in the error correction data storing cells at respective designated write addresses of the memory cell array; and

written data selecting means, responsive to a write control signal, for selectively applying the error correction data and a part of the information data to the writing means, as the data to be written in the error correction data storing cells, the amount of the part being equal to the second amount.

2. A device according to claim 1, wherein the written data selecting means comprises a first input system for accepting the error correction data and a second input system for accepting the information data, the written data selection means, responsive to the write control signal, selectively applying the data accepted by the first and second input systems to the writing means, as the data to be written in the error correction data storing cells.

3. A device according to claim 1, wherein the accepting means is an input buffer, and a part of the information data is supplied, via the input buffer, to the second input system.

4. A semiconductor memory device, comprising:

a memory cell array formed by arranging memory cells composed of information data storing cells and error correction data storing memory cells;

output means for outputting read data to outside;

reading means for reading first data of a first amount stored in the information data storing cells at designated read addresses of the memory cell array and second data stored in the error correction data storing cells at the designated read addresses, error correction data of a second amount being less than the first amount and a part of the first data being selectively stored as the second data, the amount of the part being equal to the second amount;

error inspecting and correcting means for inspecting error of the read first data on the basis of the read second data, and correcting the read first data if erroneous, thus outputting the read first data as is or the corrected data; and

output data selecting means, responsive to an output control signal, for selectively applying the data output from the error inspecting and correcting means and the read second data to the output means, as the read data.

5. A device according to claim 4, wherein the output data selecting means comprises a first input system for accepting the data output from the error inspecting and correcting means and a second input system for accepting the data output from the error inspecting and correcting means, the output data selection means, responsive to the output control signal, selectively applying the data accepted by the first and second input systems to the output means, as the read data.

6. A device according to claim 5, wherein the output means is an output buffer, and a part of the data accepted by the second input system is outputted outside via the output buffer.

7. A semiconductor memory device, comprising:

a memory cell array formed by arranging memory cells composed of information data storing cells and error correction data storing memory cells;

accepting means for accepting information data of a first amount;

error correction data forming means for forming error correction data of a second amount less than the first amount and related to the information data inputted from the accepting means;

writing means for storing data to be written in the information data storing cells and data to be written in the error correction data storing cells at respective designated write addresses of the memory cell array;

written data selecting means, responsive to a write control signal, for selectively applying the error correction data and a part of the information data to the writing means, as the data to be written in the error correction data storing cells, the amount of the part being equal to the second amount;

output means for outputting read data to outside;

reading means for reading data stored in the information data storing cells at the addresses of the memory cell array and data stored in the error correction data storing cells at the addresses;

error inspecting and correcting means for inspecting error of the data read from the information data storing cells on the basis of the data read from the error correction data storing cells, and correcting the data read from the information data storing cells if erroneous, thus outputting the data read from the information data storing cells as is or the corrected data; and

output data selecting mens, responsive to an output control signal, for selectively applying the data output from the error inspecting and correcting means and the data read from the error correction data storing cells to the output means, as the read data.

8. A method of writing data in a semiconductor memory device comprising a memory cell array formed by arranging memory cells composed of information data storing cells and error correction data storing memory cells, the method comprising the steps of:

inputting information data of a first amount in the semiconductor memory device;

forming error correction data of a second amount less than the first amount and related to the information data;

selecting data to be written in the error correction data storing memory cells from a part of the information data and error correction data in response to a write control signal, the amount of the part being equal to the second amount; and

storing the information data and the selected data in the information data storing cells and the error correction data storing cells, respectively at respective designated write addresses of the memory cell array.

9. A method of outputting data from a semiconductor memory device comprising a memory cell array formed by arranging memory cells composed of information data storing cells and error correction data storing memory cells, the method comprising the steps of:

reading first data of a first amount stored in the information data storing cells at designated read addresses of the memory cell array and second data stored in the error correction data storing cells at the designated read addresses, error correction data of a second amount being less than the first amount and a part of the first data being selectively stored as the second data, the amount of the part being equal to the second amount;

inspecting error of the read first data on the basis of the read second data, and correcting the read first data if erroneous, thus outputting the read first data as is or the corrected data; and

selectively outputting the data output from the error inspecting and correcting means and the read second data in response to an output control signal.

10. A method of writing data in and outputting the data from a semiconductor memory device comprising a memory cell array formed by arranging memory cells composed of information data storing cells and error correction data storing memory cells, the method comprising the steps of:

inputting information data of a first amount in the semiconductor memory device;

forming error correction data of a second amount less than the first amount and related to the information data;

selecting data to be written in the error correction data storing memory cells from a part of the information data and error correction data in response to a write control signal, the amount of the part being equal to the second amount;

storing the information data and the selected data in the information data storing cells and the error correction data storing cells, respectively at respective designated write addresses of the memory cell array;

reading the data stored in the information data storing cells at the addresses of the memory cell array and the data stored in the error correction data storing cells at the addresses;

inspecting error of the data read from the information data storing cells on the basis of the data read from the error correction data storing cells, and correcting the data read from the information data storing cells if erroneous, thus outputting the data read from the information data storing cells as is or the corrected data; and

selectively outputting the data output from the error inspecting and correcting means and the data read from the error correction data storing cells in response to an output control signal.