Power supply interruption detection and response system for a microcontroller

• US 5,428,252 A
• Filed: 01/03/1992
• Issued: 06/27/1995
• Est. Priority Date: 01/03/1992
• Status: Expired due to Term

• Current Assignee: IXYS Intl Limited (Littelfuse Incorporated)
• Original Assignee: ZiLOG Incorporated (Littelfuse Incorporated)
• Inventors: Walker, Andre B., So, Victor
• Primary Examiner(s): Young, Brian K.
• Assistant Examiner(s): Fleming, Fritz M.
• Application Number:
  US07/817,465
• Time in Patent Office: 1,271 Days
• Field of Search: 307/66, 307/64, 395/750, 340/636, 364/707, 365/228, 365/229, 365/227
• US Class Current: 307/64
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: H02J 9/061 for DC powered loads
• CPC Class Codes: Y02B 70/30 Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
• CPC Class Codes: Y04S 20/20 End-user application control systems

Abstract

A microcontroller power management system wherein the voltage of a power supply is monitored and the microcontroller central processing unit ("CPU") receives an interrupt signal when the supply voltage falls below a predetermined level. The CPU monitors the duration of the low voltage condition and switches into a sleep mode, after storing any data in its registers that are not maintained in the sleep mode, when that duration exceeds a fixed limit that indicates more than a temporary power glitch is being experienced. If only a short power glitch, the CPU continues normal operation. A large capacitor connected to the power supply input to the microcontroller provides enough energy for the microcontroller to operate normally during short glitches and to operate in a sleep mode for a considerable time, thereby maintaining data in CMOS static RAM until power is restored. This is particularly useful for battery operated systems, responding to both a low battery voltage condition and to a complete loss of power during battery replacement.

Claims

1. A power management system as part of a microcontroller, said microcontroller having a voltage supply input adapted to be connected with a power supply terminal, and having both a normal operating mode and a sleep mode, said system comprising:

means operably connected to said microcontroller power supply terminal for issuing a warning signal when a voltage level at said terminal falls below a predetermined level,

a single short term source of an operating voltage connected to said microcontroller voltage supply input, said short term source being devoid of a backup battery supply, and

means controlling operation of the microcontroller and responsive to said warning signal for continuing the microcontroller'"'"'s said normal operating mode when said warning signal has a duration of less than a predetermined time, wherein said short term operating voltage source is adequate to maintain the normal operating mode, and for switching into the microcontroller'"'"'s sleep mode when said warning signal has a duration of more than said predetermined time, wherein said short term operating voltage source is adequate to maintain the sleep mode for a time,

wherein said microcontroller operation controlling means is also responsive to said warning signal having a duration of more than said predetermined time for copying at least some contents of dynamically refreshed volatile memory into static volatile memory prior to the microcontroller switching into its sleep mode.

2. The system according to claim 1 wherein said warning signal issuing means includes a reference voltage source related to said predetermined level and a comparator having a first input operably connected to said reference voltage source and a second input operably connected to said power supply terminal, an output of said comparator providing said warning signal when the second input voltage is less than the first input voltage.

3. The system according to claim 2 wherein said reference voltage source includes a series circuit of a Zener diode and a resistance connected between said power supply terminal and ground potential, a node between said resistance and said diode being connected to said first comparator input, thereby to provide said reference voltage.

4. The system according to claim 3 wherein said warning signal issuing means additionally includes a series circuit of two additional series resistances connected between said power supply terminal and ground potential, a node of connection between them being connected to said second comparator input.

5. The system according to claim 1 wherein said short term operating voltage source includes a capacitor connected between said microcontroller voltage supply input and ground potential.

6. The system according to claim 5 wherein said microcontroller power supply input is connected to said power supply terminal through a blocking diode.

7. The system according to claim 1 wherein said microcontroller operation controlling means includes means for accumulating a number of N times said warning signal occurs with a duration of less than said predetermined time, said number of N times being adjustably related to the length of typical power glitches which are desired to be ignored, and also being adjustably related to a storage capacity of said short term source.

8. The system according to claim 7 wherein said microcontroller contains a hardwired interrupt input to immediately detect issuance of said warning signal.

9. The system according to claim 1 wherein said microcontroller operation controlling means is also responsive to said warning signal having a duration of more than said predetermined time for issuing a power failure signal external of said microcontroller, whereby said power failure signal is used to cause other integrated circuit chips to switch into their respective sleep modes.

10. The system of claim 1 wherein said predetermined time is in the range of 1-5 milliseconds.

11. A circuit for detecting changes in the power delivered to an associated microprocessor by a primary power source, said circuit being fabricated on a semiconductor chip, said circuit comprising:

a first node having a first voltage for providing a reference voltage;

a second node having a second voltage responsive to the input voltage delivered by the primary power source;

comparator means for comparing said first voltage to said second voltage, said comparator means issuing a first signal to the microprocessor when said second voltage is less than or equal to said first voltage;

a single short term source of an operating voltage connected to a voltage supply input of said microprocessor, said short term source adapted to maintain a normal operating mode of said microprocessor for a time, said short term source further adapted to maintain a sleep mode of said microprocessor for another time, said short term source further being devoid of a backup battery supply; and

memory means including static volatile memory for copying and storing at least some contents of dynamically refreshed volatile memory into said static volatile memory.

12. A power management system for use with a microprocessor, said microprocessor being fabricated on an integrated circuit and being powered by an external power source, said system comprising:

a first node having a first voltage for providing a reference voltage;

a second node having a second voltage responsive to the input voltage delivered by the power source;

comparator means for comparing said first voltage to said second voltage, said comparator means issuing a first signal to a microprocessor when said second voltage is less than or equal to said first voltage;

a single short term source of an operating voltage connected to a voltage supply input of said microprocessor, said short term source adapted to maintain a normal operating mode of said microprocessor for a time, said short term source further adapted to maintain a sleep mode of said microprocessor for another time, said short term source further being devoid of a backup battery supply;

diode means for separating said short term source from said first node and said second node such that said nodes may accurately detect a drop in or loss of input power;

means responsive to the occurrence of said first signal for periodically checking said first signal in order to determine its duration; and

means including a static volatile memory, and responsive to said checking means for copying and storing at least some contents of temporary registers into said static volatile memory if the first signal continues in excess of a preset amount of time.

13. A method for managing a computer system when a supply voltage to the system falls below a predetermined level, said system having a microcontroller, said microcontroller including a voltage supply input adapted to be connected with a power supply terminal, and having both a normal operating mode and a sleep mode, said system further including a single short term source of an operating voltage connected to said microcontroller voltage supply input, said short term source being devoid of a battery backup power source, said method comprising the steps of:

(a) comparing a voltage level at a reference voltage source to a voltage level at said power supply terminal;

(b) issuing a warning signal in response to said comparison when the voltage level at said terminal falls below the voltage level at said reference voltage source;

(c) supplying said short term source operating voltage to said microcontroller to maintain said normal operating mode while said warning signal has a duration of less than a predetermined time;

(d) copying at least some contents of dynamically refreshed volatile memory into static volatile memory prior to switching said microcontroller into its sleep mode,

(e) switching said microcontroller into its sleep mode when said warning signal has a duration of more than a predetermined time, and

(f) supplying said short term source operating voltage to said microcontroller voltage supply input to maintain said sleep mode for a time.

14. The method of claim 13 wherein said predetermined time is in the range of 1-5 milliseconds.

15. A method for managing a computer system when a supply voltage to the system falls below a predetermined level, said system having a microcontroller, said microcontroller having both a normal operating mode and a sleep mode, wherein said microcontroller includes a voltage supply input adapted to be connected with a primary power supply terminal, and further includes a comparator having a first input operably connected to a reference voltage source which is related to said predetermined level and a second input operably connected to said power supply terminal, said system further including a single short term source of an operating voltage connected to said voltage supply input of the microcontroller, said short term source being devoid of a battery backup power source, said method comprising the steps of:

(a) receiving a warning signal issued by said comparator, said warning signal indicating that the primary supply voltage to the system has fallen below said predetermined level;

(b) supplying said short term source operating voltage to said microcontroller to maintain said normal operating mode;

(c) checking to see if the warning signal is still being issued by said comparator;

(d) accumulating a number of N times that said warning signal has been checked;

(e) returning to step (c) if the accumulated number N of step (c) is less than a predetermined value;

(f) if the accumulated number N is at least equal to said predetermined value, copying at least some contents of dynamically refreshed volatile memory into static volatile memory prior to switching said microcontroller into its sleep mode;

(g) switching said microcontroller into its sleep mode when the accumulated number N is at least equal to said predetermined value; and

(h) supplying said short term source operating voltage to said microcontroller to maintain said sleep mode for a time,

16. The method of claim 15 further comprising the step of issuing a power failure signal external of said microcontroller prior to switching said microcontroller into its sleep mode, whereby said power failure signal is used to cause other integrated circuit chips to switch into their respective sleep modes.

17. A power management system as part of a microcontroller, said microcontroller having a voltage supply input adapted to be connected with a power supply terminal, and having both a normal operating mode and a sleep mode, said system comprising:

means operably connected to said microcontroller power supply terminal for issuing a warning signal when a voltage level at said terminal falls below a predetermined level,

a single short term source of an operating voltage connected to said microcontroller voltage supply input, said short term source being devoid of a backup battery supply;

means controlling operation of the microcontroller and responsive to said warning signal for continuing the microcontroller'"'"'s said normal operating mode when said warning signal has a duration of less than a predetermined time, wherein said short term operating voltage source is adequate to maintain the normal operating mode, and for switching into the microcontroller'"'"'s sleep mode when said warning signal has a duration of more than said predetermined time, wherein said short term operating voltage source is adequate to maintain the sleep mode for a time,

said microcontroller including a hardwired interrupt input to immediately detect issuance of said warning signal,

said microcontroller operation controlling means including means for accumulating a number of N times said warning signal occurs with a duration of less than said predetermined time, said number of N times being adjustably related to the length of typical power glitches which are desired to be ignored, and also being adjustably related to a storage capacity of said short term source,

wherein said microcontroller operation controlling means is also responsive to said warning signal having a duration of more than said predetermined time for copying at least some contents of dynamically refreshed volatile memory into static volatile memory prior to the microcontroller switching into its sleep mode, and

wherein said microcontroller operation controlling means is also responsive to said warning signal having a duration of more than said predetermined time for issuing a power failure signal external of said microcontroller, whereby said power failure signal is used to cause other integrated circuit chips to switch into their respective sleep modes.