Indication of data blocks in a frame received by a mobile phone
First Claim
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1. An apparatus in a mobile phone comprising:
- a counter circuit to count a plurality of received data blocks contained in a frame;
a 3/5-voting logic element operating on five of the plurality of received data blocks, wherein the 3/5 voting logic element receives the plurality of received data blocks as a data flow when the 3/5 voting logic element is selected with a bit enable signal, the 3/5 voting logic element performing a 3/5 voting process, producing a voting result and an output data stream at the end of the 3/5 voting process;
a BCH decoding circuit having an input and output, the input being connected to the voting result and the output being a received data frame syndrome;
a correction device having an input and a first and second output, the input being connected to the received data frame syndrome, the first output being a decoding result and the second output being a bit correction signal;
a data buffer having an output and a plurality of inputs, a first one of the plurality of inputs being connected to the output data stream of the 3/5 voting logic element and a second one of the plurality of inputs being connected to the bit correction signal, the data buffer producing at its output a data stream of corrected data; and
a receiver timer connected to the BCH-decoding circuit, 3/5-voting logic element and data buffer, which produces timing information for the BCH-decoding circuit, the 3/5-voting logic element, and the data buffer.
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Abstract
The inventive data decoding system provides 3/5 voting on data blocks (1 . . . 11) received in a frame. A counter circuit of the system counts the bits in the data blocks and raises a repeat flag (RFLAG) at the end of each data block. The RFLAG signal causes an interrupt in a controlling processor, enabling the processor to monitor and control the receiving synchronism. The inventive procedure can be used on Forward Control Channel (FOCC) and Forward Voice Channel (FVC) channels in the Total Access Communication System (TACS) or the Advanced Mobile Phone Services (AMPS) mobile phone systems.
54 Citations
20 Claims
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1. An apparatus in a mobile phone comprising:
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a counter circuit to count a plurality of received data blocks contained in a frame; a 3/5-voting logic element operating on five of the plurality of received data blocks, wherein the 3/5 voting logic element receives the plurality of received data blocks as a data flow when the 3/5 voting logic element is selected with a bit enable signal, the 3/5 voting logic element performing a 3/5 voting process, producing a voting result and an output data stream at the end of the 3/5 voting process; a BCH decoding circuit having an input and output, the input being connected to the voting result and the output being a received data frame syndrome; a correction device having an input and a first and second output, the input being connected to the received data frame syndrome, the first output being a decoding result and the second output being a bit correction signal; a data buffer having an output and a plurality of inputs, a first one of the plurality of inputs being connected to the output data stream of the 3/5 voting logic element and a second one of the plurality of inputs being connected to the bit correction signal, the data buffer producing at its output a data stream of corrected data; and a receiver timer connected to the BCH-decoding circuit, 3/5-voting logic element and data buffer, which produces timing information for the BCH-decoding circuit, the 3/5-voting logic element, and the data buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus in a mobile phone comprising:
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a counter circuit to count a plurality of received data blocks contained in a frame, wherein a selected number of the plurality of data blocks forms a set, the selected number preferably being five data blocks; a 3/5-voting logic element operating on five of the plurality of received data blocks, wherein the 3/5 voting logic element receives the plurality of received data blocks as a data flow when the 3/5 voting logic element is selected with a bit enable signal, the 3/5 voting logic element performing a 3/5 voting process, producing a voting result and an output data stream at the end of the 3/5 voting process; a BCH decoding circuit having an input and output, the input being connected to the voting result and the output being a received data frame syndrome; a correction device having an input and a first and second output, the input being connected to the received data frame syndrome, the first output being a decoding result and the second output being a bit correction signal; a data buffer having an output and a plurality of inputs, a first one of the plurality of inputs being connected to the output data stream of the 3/5 voting logic element and a second one of the plurality of inputs being connected to the bit correction signal, the data buffer producing at its output a data stream of corrected data; and a receiver timer connected to the BCH-decoding circuit, 3/5-voting logic element and data buffer, which produces timing information for the BCH-decoding circuit, the 3/5-voting logic element and the data buffer. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification