Data processing system simultaneously performing plural translations of virtual addresses having different page sizes

• US 5,430,856 A
• Filed: 12/14/1992
• Issued: 07/04/1995
• Est. Priority Date: 12/12/1991
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kinoshita, Koji
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): WHITFIELD, MICHAEL
• Application Number:
  US07/989,829
• Time in Patent Office: 932 Days
• Field of Search: 395/400
• US Class Current: 711/209
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/652 Page size control

Abstract

A data processing system which is capable of performing simultaneously multiple address translation of logical addresses of different page sizes into corresponding physical addresses. The system includes a processor, a main storage area, which is logically partitioned into a number of partial spaces, and an address translation controller for translating logical addresses output by the processor to physical addresses which correspond to partial spaces of the main storage area.

Claims

1. A data processing system comprising:

a processor for processing data;

a memory, coupled to said processor and logically partitioned into a plurality of partial spaces, for storing vector data; and

an address translation controller, coupled to said processor and memory, for simultaneously translating a plurality of logical addresses of different sizes of pages output by said processor to physical addresses corresponding to the partial spaces of said memory.

2. The data processing system as defined in claim 1, wherein said processor outputs control data for accessing a desired set of vector data that is stored in said memory and wherein said address translation controller comprises:

registers, coupled to said processor, for storing said control data; and

means, coupled to said registers and responsive to said control data, for determining whether said desired set of vector data corresponds to more than one of said partial spaces of said memory.

3. The data processing system as defined in claim 2, wherein said address translation controller further comprises:

means, coupled to said processor and responsive to said control data, for generating physical base addresses corresponding to said desired set of vector data; and

means, responsive to said physical base addresses and control data, for generating a plurality of physical addresses corresponding to said partial spaces of said memory where said desired set of vector data is stored.

4. The data processing system as defined in claim 3, wherein said control data comprises leading address data, between-elements distance data, and a number of elements data, and said registers comprises first, second, and third registers for storing said leading address data, between-elements distance data, and number of elements data, respectively.

5. The data processing system as defined in claim 3, wherein said control data comprises leading address data and between-elements distance data, and said registers comprises first and second registers for storing said leading address data and between-elements distance data, respectively.

6. A data processing system comprising:

storage means, logically partitioned into a plurality of partial spaces, for storing vector data comprising a plurality of elements;

a plurality of address translation buffers, logically partitioned into a plurality of pages of predetermined sizes corresponding to respective ones of said partial spaces, for translating a logical page number for each partial space to a physical page address;

address translation controller including means for, when said vector data stored in said storage means is to be accessed and if said plurality of elements of said vector data are within a range of predetermined number of pages, searching a plurality of entries in said address translation buffers, means for performing simultaneous address translation of a plurality of pages of different sizes and means for accessing the vector data; and

access element number determining means for determining the number of simultaneously accessible elements on the basis of the between-elements distance of said vector data and a page size of the partial space where desired vector data is stored.

7. A data processing system, as claimed in claim 6, wherein said access element number determining means determines, if the page size to which a leading element of said vector data is the smallest, a number of elements to be simultaneously accessed on the basis of said page size and accesses all the elements for that determined number of elements.

8. A data processing system comprising:

storage means, logically partitioned into a plurality of partial spaces, for storing vector data comprising a plurality of elements;

a plurality of address translation buffers, logically partitioned into a plurality of pages of predetermined sizes corresponding to respective ones of said partial spaces, for translating a logical page number for each partial space to a physical page address;

an address translation controller including means for, when said vector data stored in said storage means is to be accessed and if said plurality of elements of said vector data are within a range of a predetermined number of pages, searching a plurality of entries in said address translation buffers, means for performing simultaneous address translation of a plurality of pages of different sizes and means for accessing the vector data; and

access element number determining means for determining a number of simultaneously accessible elements on the basis of a between-elements distance of said vector data and a page size of partial space where desired vector data is stored, wherein

said access element number determining means includes detecting means for detecting a consecutive arrangement of said vector data over a plurality of partial spaces and, if the page size of the partial space corresponding to the leading element is found greater than that of the page of the partial space corresponding to any other element, performs access by the number of elements determined on the basis of the page size of the partial space corresponding to the leading element as long as the page sizes of all the partial spaces corresponding to the elements to be simultaneously accessed are equal to that of the page of the partial space corresponding to the leading element.