Partially-molded, PCB chip carrier package for certain non-square die shapes

• US 5,434,750 A
• Filed: 06/18/1993
• Issued: 07/18/1995
• Est. Priority Date: 02/07/1992
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Chia, Chok J., Rostoker, Michael D., Lim, Seng-Sooi
• Primary Examiner(s): Thompson, Gregory D.
• Application Number:
  US08/079,499
• Time in Patent Office: 760 Days
• Field of Search: 174/16.3, 174/52.2, 174/52.4, 257/666-679, 257/700, 257/724, 257/730, 257/737, 257/787, 257/793, 257/796-797, 361/704, 361/709, 361/717, 361/728, 361/761, 361/764, 361/774, 361/776, 361/784, 361/792, 439/55, 439/68, 439/70
• US Class Current: 361/784
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49517 Additional leads
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49558 Insulating layers on lead frames, e.g. bridging members
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10155 : being other than a cuboid
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Abstract

A dambar-less leadframe is sandwiched between two printed circuit boards (PCBs). The PCBs form a major portion of the package body, and isolate the leadframe leads from plastic molding compound. In one embodiment, an upper PCB (substrate) is formed as a ring, having an opening containing a heat sink element. A lower PCB is also formed as a ring, and has a smaller opening for receiving a die. The back face of the die is mounted to the heat sink. The exposed front face of the die is wire bonded to inner ends of conductive traces on the exposed face of the lower PCB. The outer ends of the traces are electrically connected to the leadframe leads by plated-through vias extending through the two PCBs. The plated-through vias additionally secure the sandwich structure together. Plastic molding compound is injection/transfer molded over the front face of the die and the bond wires, forming a partially-molded package. In another embodiment, the upper PCB is a solid planar element. The back face of the die is mounted to the inside surface of the upper PCB. The die, die-receiving area, and/or package body shape have a "certain non-square" shape (i.e., triangle, trapezoid, parallelogram, greatly-elongated rectangle, etc.).

Claims

1. Chip carrier package, comprising:

an upper substrate having an upper surface,a lower surface, and an outline shape;

a lower substrate having an upper surface, a lower surface, and an outline shape;

a "certain non-square" shaped opening extending through the lower substrate;

a leadframe interposed between the lower surface of the upper substrate and the upper surface of the lower substrate, the leadframe contacting the lower surface of the upper substrate and the upper surface of the lower substrate, and having leads extending from an outer periphery of the lower substrate towards the opening in the lower substrate;

wiring traces disposed on the lower surface of the lower substrate, and extending from an outer periphery of the lower substrate to adjacent the opening in the lower substrate, said wiring traces having inner ends adjacent the opening in the lower substrate;

the inner ends of said wiring traces defining a "certain non-square" die-receiving area for mounting a semiconductor die;

a semiconductor die having a front face containing circuit elements and a back face, and mounted in the opening in the lower substrate;

means for electrically connecting the circuit elements to the inner ends of the wiring traces;

means for electrically connecting outer portions of the wiring traces to the leadframe leads; and

plastic molding compound disposed over the front face of the die and extending partially over the lower surface of the lower substrate.

2. Chip carrier package, according to claim 1, wherein:

the means for electrically connecting the circuit elements to inner ends of the wiring traces is bond wires.

3. Chip carrier package, according to claim 1, wherein:

the means for electrically connecting the outer portions of the wiring traces to the leadframe leads is at least one row of plated through holes extending through outer peripheral portions of the upper and lower substrates.

4. Chip carrier package, according to claim 3, wherein:

at least two rows of plated through holes are disposed about the outer peripheral portions of the upper and lower substrates, and each row of through holes is offset from the remaining rows of plated through holes.

5. Chip carrier package, according to claim 3, further comprising:

additional through holes extending through the upper and lower substrates;

wherein;

the additional through holes are plated; and

the additional through holes are electrically isolated from the leadframe leads.

6. Chip carriers package, according to claim 1, wherein:

the upper substrate is provided with a central opening;

a heatsink element is disposed within the central opening in the upper substrate; and

the back face of the semiconductor die is adhered to the heatsink.

7. Chip carrier package, according to claim 1, wherein:

the back face of the semiconductor die is adhered to the lower surface of the upper substrate.

8. Chip carrier package, according to claim 1, wherein:

the die-receiving area has a certain non-square geometric configuration similar to a geometric configuration of a certain non-square die mounted in the die-receiving area.

9. Chip carrier package, according to claim 1, wherein:

the geometric configuration formed by the inner ends of the wiring traces defines a triangular shaped die-receiving area.

10. Chip carrier package, according to claim 1, wherein:

the geometric configuration formed by the inner ends of the wiring traces defines a "greatly elongated rectangular" shaped die-receiving area.

11. Chip carrier package, according to claim 1, wherein:

the geometric configuration formed by the inner ends of the wiring traces defines a parallelogram shaped die-receiving area.

12. Chip carrier package, according to claim 1, wherein:

the geometric configuration formed by the inner ends of the wiring traces define a trapezoidal shaped die-receiving area.

13. Chip carrier package, according to claim 1, further comprising:

a "certain non-square" body shape defined by the outlines of the upper and lower substrates.

14. Chip carrier package, according to claim 13, wherein:

the body shape is triangular.

15. Chip carrier package, according to claim 13, wherein:

the body shape is a "greatly elongated rectangular" shape.

16. Chip carrier package, according to claim 13, wherein:

the body shape is a parallelogram shape.

17. Chip carrier package, according to claim 13, wherein:

the body shape is a trapezoidal shape.

18. Chip carrier comprising:

an upper substrate having an upper surface, a lower surface, and an outline;

a lower substrate having an upper surface, a lower surface, and an outline;

a "certain non-square" shaped opening extending through the lower substrate for receiving a semiconductor die;

a leadframe interposed between the lower surface of the upper substrate and the upper surface of the lower substrate, the leadframe contacting the lower surface of the upper substrate and the upper surface of the lower substrate, and having leads extending from an outer periphery of the lower substrate towards the opening in the lower substrate;

wiring traces disposed on the lower surface of the lower substrate, and extending from an outer periphery of the lower substrate to adjacent the opening in the lower substrate, said wiring traces having inner ends adjacent the opening in the lower substrate;

the inner ends of said wiring traces defining a "certain non-square" die-receiving area for mounting a semiconductor die; and

means for electrically connecting outer portions of the wiring traces to the leadframe leads;

wherein;

a completed package is formed by mounting a die in the opening, connecting the die to the inner ends of the wiring traces and disposing plastic molding compound over the die and partially over the lower surface of the lower substrate.