Data processing apparatus having first bus with bus arbitration independent of CPU, second bus for CPU, and gate between first and second buses

• US 5,434,983 A
• Filed: 08/28/1992
• Issued: 07/18/1995
• Est. Priority Date: 08/30/1991
• Status: Expired due to Fees

• Current Assignee: Matsushita Graphic Communication Systems, Inc. (Panasonic Holdings Corporation)
• Original Assignee: Fujitsu Limited
• Inventors: Hagiwara, Takashi, Yaso, Kenji
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US07/936,945
• Time in Patent Office: 1,054 Days
• Field of Search: 395/325, 395/275, 395/425, 395/800, 395/725, 395/200, 340/825.5, 370/85.2, 364/514, 358/442
• US Class Current: 710/110
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4031 with arbitration

Abstract

An image processing apparatus containing a first bus, a second bus, a CPU connected to the first bus, a plurality of bus user units respectively connected to the second bus, a bus control unit connected with each of the plurality of bus user units and the CPU, and a bus connect/isolate gate unit connected with the first and second buses and the bus control unit. Each of the plurality of bus user units and the CPU contains a bus request signal sending unit for sending a bus request signal to the bus control unit when each of the plurality of bus user units and the CPU has a demand to use the second bus. The bus connect/isolate gate unit can isolate the first bus from the second bus, or connect the first bus with the second bus, under control of the bus control unit. The bus control unit receives the bus request signal from each of the plurality of bus user units and the CPU, determines one of the plurality of bus user units and the CPU, which sends the bus request signal to the bus control unit, as an acknowledged unit, sends an acknowledge signal to the acknowledged unit, makes the bus connect/isolate gate connect the first bus with the second bus when the CPU is the acknowledged unit, and makes the bus connect/isolate gate isolate the first bus from the second bus when the CPU is not the acknowledged unit.

Claims

1. A processing apparatus comprising:

a first bus;

a second bus;

a central processing unit connected to the first bus;

a plurality of bus slave units respectively connected to the second bus;

memory means, connected to the second bus, for storing data;

second-bus control means connected with each of the plurality of bus slave units and the central processing unit; and

bus connect/isolate gate means connected with the first and second buses and the second-bus control means,

said central processing unit comprising a bus request signal sending means for sending a bus request signal to the second-bus control means when the central processing unit has a demand to use the second bus,

each of the plurality of bus slave units comprising a data transfer request signal sending means for sending a data transfer request signal to the second-bus control means when each of the plurality of bus slave units has a demand to transmit or receive data through the second bus,

said bus connect/isolate gate means being able to isolate the first bus from the second bus, or to connect the first bus with the second bus, under control of the second-bus control means,

said second-bus control means comprising;

request signal receiving means for receiving the bus request signal from the central processing unit and the data transfer request signals from the plurality of bus slave units;

acknowledged unit determining means for determining one of the central processing unit which sends the bus request signal and the plurality of bus slave units which send the data transfer request signals, as an acknowledged unit;

acknowledge signal sending means for sending an acknowledge signal to said acknowledged unit;

gate control means for making the bus connect/isolate gate connect the first bus with the second bus when the central processing unit is the acknowledged unit, and making the bus connect/isolate gate isolate the first bus from the second bus when the central processing unit is not the acknowledged unit; and

DMA control means, connected to the second bus, for controlling the memory means so that data transfer between the memory means and said acknowledged unit is performed through said second bus by a direct memory access operation when said acknowledged unit determining means determines one of the bus slave units as the acknowledged unit.

2. A processing apparatus comprising:

a first bus;

a second bus;

a central processing unit connected to the first bus;

a plurality of bus slave units respectively connected to the second bus;

memory means, connected to the second bus, for storing data;

second-bus control means connected with each of the plurality of bus slave units and the central processing unit; and

bus connect/isolate gate means connected with the first and second buses and the second-bus control means,

said central processing unit comprising a bus request signal sending means for sending a bus request signal to the second-bus control means when the central processing unit has a demand to use the second bus,

each of the plurality of bus slave units comprising a data transfer request signal sending means for sending a data transfer request signal to the second-bus control means when each of the plurality of bus slave units has a demand to transmit or receive data through the second bus,

said bus connect/isolate gate means being able to isolate the first bus from the second bus, or to connect the first bus with the second bus, under control of the second-bus control means,

said second-bus control means comprising;

request signal receiving means for receiving the bus request signal from the central processing unit and the data transfer request signals from the plurality of bus slave units;

acknowledged unit determining means for determining one of the central processing unit which sends the bus request signal and the plurality of bus slave units which send the data transfer request signals, as an acknowledged unit;

acknowledge signal sending means for sending an acknowledge signal to said acknowledged unit;

gate control means for making the bus connect/isolate gate connect the first bus with the second bus when the central processing unit is the acknowledged unit, and making the bus connect/isolate gate isolate the first bus from the second bus when the central processing unit is not the acknowledged unit; and

DMA control means, connected to the second bus, for controlling the memory means so that data transfer between the memory means and said acknowledged unit is performed through said second bus by a direct memory access operation when said acknowledged unit determining means determines one of the bus slave units as the acknowledged unit, wherein;

the operation of said acknowledged unit determining means is performed periodically; and

said processing apparatus further comprises latch means for latching information on the acknowledged unit determined by the acknowledged unit determining means, for each period of the operation of said acknowledged unit determining means, and supplying the latched information to said DMA control means, said acknowledge signal sending means, and said gate control means.

3. A processing apparatus comprising:

a first bus;

a second bus;

a central processing unit connected to the first bus;

a plurality of bus slave units respectively connected to the second bus;

memory means, connected to the second bus, for storing data;

second-bus control means connected with each of the plurality of bus slave units and the central processing unit; and

bus connect/isolate gate means connected with the first and second buses and the second-bus control means,

said central processing unit comprising a bus request signal sending means for sending a bus request signal to the second-bus control means when the central processing unit has a demand to use the second bus,

each of the plurality of bus slave units comprising a data transfer request signal sending means for sending a data transfer request signal to the second-bus control means when each of the plurality of bus slave units has a demand to transmit or receive data through the second bus,

said bus connect/isolate gate means being able to isolate the first bus from the second bus, or to connect the first bus with the second bus, under control of the second-bus control means,

said second-bus control means comprising;

request signal receiving means for receiving the bus request signal from the central processing unit and the data transfer request signals from the plurality of bus slave units;

acknowledged unit determining means for determining one of the central processing unit which sends the bus request signal and the plurality of bus slave units which send the data transfer request signals, as an acknowledged unit;

acknowledge signal sending means for sending an acknowledge signal to said acknowledged unit;

gate control means for making the bus connect/isolate gate connect the first bus with the second bus when the central processing unit is the acknowledged unit, and making the bus connect/isolate gate isolate the first bus from the second bus when the central processing unit is not the acknowledged unit; and

DMA control means, connected to the second bus, for controlling the memory means so that data transfer between the memory means and said acknowledged unit is performed through said second bus by a direct memory access operation when said acknowledged unit determining means determines one of the bus slave units as the acknowledged unit, wherein said DMA control means comprises;

address generating means for generating an address signal to be supplied to the memory means for controlling the memory means in the data transfer operation, and

control signal generating means for generating control signals to be supplied to the memory means for controlling the memory means in the data transfer operation.

4. A facsimile terminal apparatus comprising,

a first bus,

a second bus,

a central processing unit connected to the first bus,

a plurality of bus slave units respectively connected to the second bus,

memory means, connected to the second bus, for storing data,

second-bus control means connected with each of the plurality of bus slave units and the central processing unit, and

bus connect/isolate gate means connected with the first and second buses and the second-bus control means,

said central processing unit comprising a bus request signal sending means for sending a bus request signal to the second-bus control means when the central processing unit has a demand to use the second bus;

each of the plurality of bus slave units comprising a data transfer request signal sending means for sending a data transfer request signal to the second-bus control means when each of the plurality of bus slave units has a demand to transmit or receive data through the second bus;

said bus connect/isolate gate means being able to isolate the first bus from the second bus, or to connect the first bus with the second bus, under control of the second-bus control means;

said second-bus control means comprising,

request signal receiving means for receiving the bus request signal from the central processing unit and the data transfer request signals from the plurality of bus slave units;

acknowledged unit determining means for determining one of the central processing unit which sends the bus request signal and the plurality of bus slave units which sends the data transfer request signal, as an acknowledged unit;

acknowledge signal sending means for sending an acknowledge signal to said acknowledged unit;

gate control means for making the bus connect/isolate gate connect the first bus with the second bus when the central processing unit is the acknowledged unit, and making the bus connect/isolate gate isolate the first bus from the second bus when the central processing unit is not the acknowledged unit;

said facsimile terminal apparatus further comprising a DMA control means for controlling the memory means so that data transfer between the memory means and said acknowledged unit is performed through said second bus by a direct memory access operation when said acknowledged unit determining means determines one of the bus slave units as the acknowledged unit;

said plurality of bus slave units including a read-in image input unit, an image output unit, a compression unit, an expansion unit, and a communication control unit;

said data transfer request signal sending means in said compression unit comprises first data transfer request signal sending means for sending a first data transfer request signal to the second-bus control means, and a second data transfer request signal sending means for sending a second data transfer request signal to the second-bus control means,

said data transfer request signal sending means in said communication control unit comprises third data transfer request signal sending means for sending a third data transfer request signal to the second-bus control means, and a fourth data transfer request signal sending means for sending a fourth data transfer request signal to the second-bus control means,

said data transfer request signal sending means in said expansion unit comprises fifth data transfer request signal sending means for sending a fifth data transfer request signal to the second-bus control means, and a sixth data transfer request signal sending means for sending a sixth data transfer request signal to the second-bus control means;

said read-in image input unit comprising,

first and second data ports,

means for inputting image data through the first data port,

first register means for temporarily holding the image data,

first detecting means for detecting a first state of the first register means, in which the first register means holds the image data,

means for receiving the acknowledge signal from said second-bus control means in response to said data transfer request signal sent from the data transfer request signal sending means in the read-in image input unit, and

means for transferring the image data to the memory means through said second data port and said second bus to which the second port is connected, to store the image data in the memory means as a first image data, when receiving said acknowledge signal by said acknowledge signal receiving means in the read-in image input unit,

said data transfer request signal sending means in said read-in image input unit sends the data transfer request signal to the second-bus control means, when said first detecting means detects said first state;

said compression unit comprising,

means for receiving a compression command from the central processing unit,

first acknowledge signal receiving means for receiving a first acknowledge signal from said second-bus control means in response to said first data transfer request signal sent from the first data transfer request signal sending means,

means for receiving the first image data transferred from the memory means through said second bus, when receiving said first acknowledge signal,

means for compressing said first image data,

second register means for temporarily holding the compressed first image data,

second detecting means for detecting a second state of the second register means, in which the second register means holds the compressed first image data,

second acknowledge signal receiving means for receiving a second acknowledge signal from said second-bus control means in response to said second data transfer request signal sent from the second data transfer request signal sending means, and

means for transferring the compressed first image data to the memory means through said second bus, to store the compressed first image data in the memory means, when receiving said second acknowledge signal,

said first data transfer request signal sending means in said compression unit sends the first data transfer request signal to the second-bus control means, when receiving said compression command, and

said second data transfer request signal sending means in said compression unit sends the second data transfer request signal to the second-bus control means, when said second detecting means detects said second state;

said communication control unit comprising,

third and fourth data ports,

transmission command receiving means for receiving a transmission command from the central processing unit,

third acknowledge signal receiving means for receiving a third acknowledge signal from said second-bus control means in response to said third data transfer request signal sent from the third data transfer request signal sending means,

means for receiving the compressed first image data transferred from the memory means through said third data port and said second bus to which the third data port is connected, when receiving said third acknowledge signal in response to said third data transfer request signal,

means for transmitting said compressed first image data through the fourth data port,

means for receiving said a compressed second image data through the fourth data port,

third register means for temporarily holding the compressed second image data,

third detecting means for detecting a third state of the third register means, in which the third register means holds the compressed second image data,

fourth acknowledge signal receiving means for receiving a fourth acknowledge signal from said second-bus control means in response to said fourth data transfer request signal sent from the fourth data transfer request signal sending means, and

means for transferring the compressed second image data to the memory means through said second bus to store the compressed second image data in the memory means, when receiving said fourth acknowledge signal,

said third data transfer request signal sending means in said communication control unit sends the third data transfer request signal to the second-bus control means, when receiving said transmission command, and

said fourth data transfer request signal sending means in said communication control unit sends the fourth data transfer request signal to the second-bus control means, when said third detecting means detects said third state;

said expansion unit comprising,

means for receiving an expansion command from the central processing unit,

fifth acknowledge signal receiving means for receiving a fifth acknowledge signal from said second-bus control means in response to said fifth data transfer request signal sent from the fifth data transfer request signal sending means,

means for receiving the compressed second image data transferred from the memory means through said second bus, when receiving said fifth acknowledge signal in response to said fifth data transfer request signal,

means for expanding said compressed second image data to generate a second image data,

fourth register means for temporarily holding the second image data,

fourth detecting means for detecting a fourth state of the fourth register means, in which the fourth register means holds the second image data,

sixth acknowledge signal receiving means for receiving a sixth acknowledge signal from said second-bus control unit in response to said sixth data transfer request signal sent from the sixth data transfer request signal sending means, and

means for transferring the second image data to the memory means through said second bus to store the second expanded image data in the memory means, when receiving said sixth acknowledge signal in response to the sixth data transfer request signal,

said fifth data transfer request signal sending means in said expansion unit sends the fifth data transfer request signal to the second-bus control means, when receiving said expansion command, and

said sixth data transfer request signal sending means in said expansion unit sends the sixth data transfer request signal to the second-bus control means, when the fourth detecting means detects the fourth state;

said image output unit comprising,

fifth and sixth data ports,

output command receiving means for receiving an output command from the central processing unit,

acknowledge signal receiving means for receiving the acknowledge signal from said second-bus control unit in response to said data transfer request signal sent from the data transfer request signal sending means in the image output input unit, and

means for receiving the second image data transferred from the memory means through said fifth data port and said second bus to which the fifth data port is connected, when receiving said acknowledge signal by the acknowledge signal receiving means in the image output unit, and

means for outputting said second image data through the sixth data port,

said data transfer request signal sending means in said image output unit sends the data transfer request signal to the second-bus control means, when receiving said output command;

said central processing unit comprising,

compression command sending means for sending the compression command to said compression unit when said first image data is stored in the memory means,

communication command sending means for sending the communication command to said communication control unit when said compressed first image data is stored in the memory means,

expansion command sending means for sending the expansion command to said expansion unit when said compressed second image data is stored in the memory means, and

output command sending means for sending the output command to said image output unit when said second image data is stored in the memory means.

5. A facsimile terminal apparatus according to claim 4, wherein the operation of said acknowledged unit determining means being performed periodically;

and

said facsimile terminal apparatus further comprising a latch means for latching information on the acknowledged unit determined by the acknowledged unit determining means, for each period of the operation of said acknowledged unit determining means, and supplying the latched information to said DMA control means, said acknowledge signal sending means, and said gate control means.

6. A facsimile terminal apparatus according to claim 4, wherein said DMA control means comprises:

address generating means for generating an address signal to be supplied to the memory means for controlling the memory means in the data transfer operation; and

control signal generating means for generating control signals to be supplied to the memory means for controlling the memory means in the data transfer operation.

7. An integrated circuit formed on a semiconductor substrate, comprising:

a first bus,

a second bus,

a first port connected to the first bus,

second, third, fourth, and fifth ports connected to the second bus,

a plurality of bus slave units respectively connected to the second bus,

second-bus control means connected with each of the plurality of bus slave units and the first port, and

bus connect/isolate gate means connected with the first and second buses and the second-bus control means,

each of the plurality of bus slave units comprising a data transfer request signal sending means for sending a data transfer request signal to the second-bus control means when each of the plurality of bus slave unit has a demand to transmit or receive data through the second bus;

said bus connect/isolate gate means being able to isolate the first bus from the second bus, or to connect the first bus with the second bus, under control of the second-bus control means;

said second-bus control means comprising;

request signal receiving means for receiving the data transfer request signal from each of the plurality of bus slave units, and a bus request signal received through the first port;

acknowledge request determining means for determining one of the data transfer request signals from the plurality of bus slave units and the bus request signal from the first port, as an acknowledged request signal;

acknowledge signal sending means for sending an acknowledge signal to one of the plurality of bus slave units and the first port, from which said one of the data transfer request signals and the bus request signal, which is determined as the acknowledged request signal in said acknowledge request determining means, is received by said request signal receiving means; and

gate control means for making the bus connect/isolate gate connect the first bus with the second bus when the acknowledge request is received from the first port, and making the bus connect/isolate gate isolate the first bus from the second bus when the acknowledge request is received from one of the plurality of bus slave units;

said integrated circuit further comprising DMA control means, connected to said second bus, for controlling memory means, when the memory means is connected to the second port, so that data transfer between the memory means and one of said bus slave units from which the acknowledged request signal is received, is performed through said second bus by a direct memory access operation when said acknowledged request determining means determines the acknowledged request signal;

said plurality of bus slave units including a read-in image input unit, an image output unit, a compression unit, an expansion unit, and a communication control unit;

said data transfer request signal sending means in said compression unit comprises first data transfer request signal sending means for sending a first data transfer request signal to the second-bus control means, and a second data transfer request signal sending means for sending a second data transfer request signal to the second-bus control means,

said data transfer request signal sending means in said communication control unit comprises third data transfer request signal sending means for sending a third data transfer request signal to the second-bus control means, and a fourth data transfer request signal sending means for sending a fourth data transfer request signal to the second-bus control means,

said data transfer request signal sending means in said expansion unit comprises fifth data transfer request signal sending means for sending a fifth data transfer request signal to the second-bus control means, and a sixth data transfer request signal to the second-bus control means;

said read-in image input unit comprising;

a sixth port connected to said third port,

a seventh port,

a means for inputting image data through the third and sixth ports,

first register means for temporarily holding the image data,

first detecting means for detecting a first state of the first register means, in which the first register means holds the image data,

means for receiving the acknowledge signal from said second-bus control means in response to said data transfer request signal sent from the data transfer request signal sending means in the read-in image input unit, and

means for transferring the image data to the memory means, when the memory means is connected to the second port, through said seventh port and said second bus to which the seventh port is connected, to store the image data in the memory means as a first image data, when receiving said acknowledge signal by said acknowledge signal receiving means in the read-in image input unit,

said data transfer request signal sending means in said read-in image input unit sends the data transfer request signal to the second-bus control means, when said first detecting means detects said first state;

said compression unit comprising;

means for receiving a compression command from the first port through the first and second buses and the bus connect/isolate means,

first acknowledge signal receiving means for receiving a first acknowledge signal from said second-bus control means in response to said first data transfer request signal sent from the first data transfer request signal sending means,

means for receiving the first image data transferred from the memory means through said second bus, when receiving said first acknowledge signal,

means for compressing said first image data,

second register means for temporarily holding the compressed first image data,

second detecting means for detecting a second state of the second register means, in which the second register means holds the compressed first image data,

second acknowledge signal receiving means for receiving a second acknowledge signal from said second-bus control means in response to said second data transfer request signal sent from the second data transfer request signal sending means, and

means for transferring the compressed first image data to the memory means, when the memory means is connected to the second port, through said second bus, to store the compressed first image data in the memory means, when receiving said second acknowledge signal,

said first data transfer request signal sending means in said compression unit sends the first data transfer request signal to the second-bus control means, when receiving said compression command, and

said second data transfer request signal sending means in said compression unit sends the second data transfer request signal to the second-bus control means, when said second detecting means detects said second state;

said communication control unit comprising,

an eighth port,

a ninth port connected to the fifth port,

transmission command receiving means for receiving a transmission command from the first port through the first and second buses and the bus connect/isolate means,

third acknowledge signal receiving means for receiving a third acknowledge signal from said second-bus control means in response to said third data transfer request signal sent from the third data transfer request signal sending means,

means for receiving the compressed first image data transferred from the memory means, when the memory means is connected to the second port, through said eighth port and said second bus to which the eighth port is connected, when receiving said third acknowledge signal in response to said third data transfer request signal,

means for transmitting said compressed first image data through the ninth and fifth ports,

means for receiving said a compressed second image data through the ninth and fifth ports,

third register means for temporarily holding the compressed second image data,

third detecting means for detecting a third state of the third register means, in which the third register means holds the compressed second image data,

fourth acknowledge signal receiving means for receiving a fourth acknowledge signal from said second-bus control means in response to said fourth data transfer request signal sent from the fourth data transfer request signal sending means, and

means for transferring the compressed second image data to the memory means through said second bus to store the compressed second image data in the memory means, when receiving said fourth acknowledge signal,

said third data transfer request signal sending means in said communication control unit sends the third data transfer request signal to the second-bus control means, when receiving said transmission command, and

said fourth data transfer request signal sending means in said communication control unit sends the fourth data transfer request signal to the second-bus control means, when said third detecting means detects said third state;

said expansion unit comprising;

means for receiving an expansion command from the first port through the first and second buses and the bus connect/isolate means,

fifth acknowledge signal receiving means for receiving a fifth acknowledge signal from said second-bus control means in response to said fifth data transfer request signal sent from the fifth data transfer request signal sending means,

means for receiving the compressed second image data transferred from the memory means, when the memory means is connected to the second port, through said second bus, when receiving said fifth acknowledge signal in response to said fifth data transfer request signal,

means for expanding said compressed second image data to generate a second image data,

fourth register means for temporarily holding the second image data,

fourth detecting means for detecting a fourth state of the fourth register means, in which the fourth register means holds the second image data,

sixth acknowledge signal receiving means for receiving a sixth acknowledge signal from said second-bus control unit in response to said sixth data transfer request signal sent from the sixth data transfer request signal sending means, and

means for transferring the second image data to the memory means through said second bus to store the second expanded image data in the memory means, when receiving said sixth acknowledge signal in response to the sixth data transfer request signal,

said fifth data transfer request signal sending means in said expansion unit sends the fifth data transfer request signal to the second-bus control means, when receiving said expansion command, and

said sixth data transfer request signal sending means in said expansion unit sends the sixth data transfer request signal to the second-bus control means, when the fourth detecting means detects the fourth state;

said image output unit comprising;

a tenth port,

an eleventh port connected to said fourth port,

output command receiving means for receiving an output command from the first port through the first and second buses and the bus connect/isolate means,

acknowledge signal receiving means for receiving the acknowledge signal from said second-bus control unit in response to said data transfer request signal sent from the data transfer request signal sending means in the image output input unit, and

means for receiving the second image data transferred from the memory means, when the memory means is connected to the second port, through said tenth port and said second bus to which the sixth port is connected, when receiving said acknowledge signal by the acknowledge signal receiving means in the image output unit, and

means for outputting said second image data through the eleventh and fourth ports,

said data transfer request signal sending means in said image output unit sends the data transfer request signal to the second-bus control means, when receiving said output command.

8. A facsimile terminal apparatus comprising:

one first and at least one second integrated circuits each formed on a semi-conductor substrate, and each of the first and at least one second integrated circuits comprising;

a first bus,

a second bus,

a first port connected to the first bus,

second, third, fourth, and sixth ports connected to the second bus,

a plurality of bus slave units respectively connected to the second bus,

second-bus control means connected with each of the plurality of bus slave units and the first port, and

bus connect/isolate gate means connected with the first and second buses and the second-bus control means;

each of the plurality of bus slave units comprising a data transfer request signal sending means for sending a data transfer request signal to the second-bus control means when each of the plurality of bus slave units has a demand to transmit or receive data through the second bus;

said bus connect/isolate gate means being able to isolate the first bus from the second bus, or to connect the first bus with the second bus, under control of the second-bus control means;

said second-bus control means comprising;

request signal receiving means for receiving the data transfer request signal from each of the plurality of bus slave units, and a bus request signal from the first port;

acknowledge request determining means for determining one of the data transfer request signals from the plurality of bus slave units and the bus request signal from the first port, as an acknowledged request signal;

acknowledge signal sending means for sending an acknowledge signal to one of the plurality of bus slave units and the first port, from which said one of the data transfer request signals and the bus request signal, which is determined as the acknowledged request signal in said acknowledge request determining means, is received by said request signal receiving means; and

gate control means for making the bus connect/isolate gate connect the first bus with the second bus when the acknowledge request is received from the first port, and making the bus connect/isolate gate isolate the first bus from the second bus when the acknowledge request is received from one of the plurality of bus slave units;

said integrated circuit further comprising a DMA control means, connected to said second bus, for controlling memory means, when the memory means is connected to the second port, so that data transfer between the memory means and one of said bus slave units from which the acknowledge request signal is received, is performed through said second bus by a direct memory access operation when said acknowledged request determining means determines the acknowledged request signal;

said plurality of bus slave units including a read-in image input unit, an image output unit, a compression unit, an expansion unit, and a communication control unit;

said facsimile terminal apparatus further comprising;

a first central processing unit connected to the first port of the first integrated circuit,

at least one second central processing unit respectively connected to the first port of each of the second integrated circuits,

first memory means connected to the first port of the first integrated circuit, and

at least one second memory means respectively connected to the first port of each of the at least one second integrated circuits;

in each of said first and at least one second integrated circuits,

said data transfer request signal sending means in said compression unit comprises first data transfer request signal sending means for sending a first data transfer request signal to the second-bus control means, and a second data transfer request signal sending means for sending a second data transfer request signal to the second-bus control means,

said data transfer request signal sending means in said communication control unit comprises third data transfer request signal sending means for sending a third data transfer request signal to the second-bus control means, and a fourth data transfer request signal sending means for sending a fourth data transfer request signal to the second-bus control means,

said data transfer request signal sending means in said expansion unit comprises fifth data transfer request signal sending means for sending a fifth data transfer request signal to the second-bus control means, and a sixth data transfer request signal sending means for sending a sixth data transfer request signal to the second-bus control means;

said read-in image input unit comprising;

a sixth port connected to said third port,

a seventh port,

means for inputting image data through the third and sixth ports,

first register means for temporarily holding the image data,

first detecting means for detecting a first state of the first register means, in which the first register means holds the image data,

means for receiving the acknowledge signal from said second-bus control means in response to said data transfer request signal sent from the data transfer request signal sending means in the read-in image input unit, and

means for transferring the image data to one of the first and at least one second memory means, which is connected to the second port of said each of the first and at least one second integrated circuits, through said seventh port and said second bus to which the seventh port is connected, to store the image data in the memory means as a first image data, when receiving said acknowledge signal by said acknowledge signal receiving means in the read-in image input unit,

said data transfer request signal sending means in said read-in image input unit sends the data transfer request signal to the second-bus control means, when said first detecting means detects said first state;

said compression unit comprising;

means for receiving a compression command from the first port through the first and second buses and the bus connect/isolate means,

first acknowledge signal receiving means for receiving a first acknowledge signal from said second-bus control unit in response to said first data transfer request signal sent from the first data transfer request signal sending means,

means for receiving the first image data transferred from the memory means through said second bus, when receiving said first acknowledge signal,

means for compressing said first image data,

second register means for temporarily holding the compressed first image data,

second detecting means for detecting a second state of the second register means, in which the second register means holds the compressed first image data,

second acknowledge signal receiving means for receiving a second acknowledge signal from said second-bus control means in response to said second data transfer request signal sent from the second data transfer request signal sending means, and

means for transferring the compressed first image data to one of the first and at least one second memory means, which is connected to the second port of said each of the first and at least one second integrated circuits, through said second bus, to store the compressed first image data in the memory means, when receiving said second acknowledge signal,

said first data transfer request signal sending means in said compression unit sends the first data transfer request signal to the second-bus control means, when receiving said compression command, and

said second data transfer request signal sending means in said compression unit sends the second data transfer request signal to the second-bus control means, when said second detecting means detects said second state;

said communication control unit comprising;

an eighth port,

a ninth port connected to the fifth port,

transmission command receiving means for receiving a transmission command from the first port through the first and second buses and the bus connect/isolate means,

third acknowledge signal receiving means for receiving a third acknowledge signal from said second-bus control unit in response to said third data transfer request signal sent from the third data transfer request signal sending means,

means for receiving the compressed first image data transferred from one of the first and at least one second memory means, which is connected to the second port of said each of the first and at least one second integrated circuits, through said eighth port and said second bus to which the eighth port is connected, when receiving said third acknowledge signal in response to said third data transfer request signal,

means for transmitting said compressed first image data through the ninth port,

means for receiving said a compressed second image data through the ninth port,

third register means for temporarily holding the compressed second image data,

third detecting means for detecting a third state of the third register means, in which the third register means holds the compressed second image data,

fourth acknowledge signal receiving means for receiving a fourth acknowledge signal from said second-bus control means in response to said fourth data transfer request signal sent from the fourth data transfer request signal sending means, and

means for transferring the compressed second image data to the memory means through said second bus to store the compressed second image data in the memory means, when receiving said fourth acknowledge signal,

said third data transfer request signal sending means in said communication control unit sends the third data transfer request signal to the second-bus control means, when receiving said transmission command, and

said fourth data transfer request signal sending means in said communication control unit sends the fourth data transfer request signal to the second-bus control means, when said third detecting means detects said third state;

said expansion unit comprising;

means for receiving an expansion command from the first port through the first and second buses and the bus connect/isolate means,

fifth acknowledge signal receiving means for receiving a fifth acknowledge signal from said second-bus control unit in response to said fifth data transfer request signal sent from the fifth data transfer request signal sending means,

means for receiving the compressed second image data transferred from one of the first and at least one second memory means, which is connected to the second port of said each of the first and at least one second integrated circuits, through said second bus, when receiving said fifth acknowledge signal in response to said fifth data transfer request signal,

means for expanding said compressed second image data to generate a second image data,

fourth register means for temporarily holding the second image data,

fourth detecting means for detecting a fourth state of the fourth register means, in which the fourth register means holds the second image data,

sixth acknowledge signal receiving means for receiving a sixth acknowledge signal from said second-bus control unit in response to said sixth data transfer request signal sent from the sixth data transfer request signal sending means, and

means for transferring the second image data to the memory means through said second bus to store the second expanded image data in the memory means, when receiving said sixth acknowledge signal in response to the sixth data transfer request signal,

said fifth data transfer request signal sending means in said expansion unit sends the fifth data transfer request signal to the second-bus control means, when receiving said expansion command, and

said sixth data transfer request signal sending means in said expansion unit sends the sixth data transfer request signal to the second-bus control means, when the fourth detecting means detects the fourth state;

said image output unit comprising;

a tenth port,

an eleventh port connected to said fourth port,

output command receiving means for receiving an output command from the first port through the first and second buses and the bus connect/isolate means,

acknowledge signal receiving means for receiving the acknowledge signal from said second-bus control unit in response to said data transfer request signal sent from the data transfer request signal sending means in the image output input unit, and

means for receiving the second image data transferred from one of the first and at least one second memory means, which is connected to the second port of said each of the first and at least one second integrated circuits, through said tenth port and said second bus to which the sixth port is connected, when receiving said acknowledge signal by the acknowledge signal receiving means in the image output unit, and

means for outputting said second image data through the eleventh and fought ports,

said data transfer request signal sending means in said image output unit sends the data transfer request signal to the second-bus control means, when receiving said output command;

said ninth port of the communication control unit in the first integrated circuit is connected to the third and fourth ports of the second integrated circuit so that the compressed image data transmitted from the communication control unit in the first integrated circuit is input through the third port of the second integrated circuit, and the image data output from the fourth port of the second integrated circuit is received through the ninth port of the communication control unit in the first integrated circuit by the communication control unit in the first integrated circuit.