Dual computer system

• US 5,434,998 A
• Filed: 03/16/1993
• Issued: 07/18/1995
• Est. Priority Date: 04/13/1988
• Status: Expired due to Fees

• Current Assignee: Yokogawa Electric Corporation
• Original Assignee: Yokogawa Electric Corporation
• Inventors: Nakamoto, Eiji, Akai, Hajime, Domoto, Isao, Morioka, Yoshitugu, Hayashi, Shunsuke
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/033,661
• Time in Patent Office: 854 Days
• Field of Search: 395/575, 364/131, 364/229.4, 364/230.5
• US Class Current: 714/11
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/2025 using centralised failover control functionality
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2048 where the redundant components share neither address space nor persistent storage

Abstract

A dual computer system comprising a pair of processor units, and a dual control unit for controlling which of the two processor units are to be kept operating or on standby in case of failure of the operated unit; wherein the dual control unit controls which processor unit is to be operated through monitoring of the operating states of the two processor units, and comprising two independent interruption devices for indicating the switching of the two processor units through interruption. The system is effective in improving the continuity of the control at the time of switching.

Claims

1. In a dual computer system comprising a left processor unit, and a right processor unit, one of said left and right processor units being operated as a main system while the other is kept on standby as a subsidiary system against the failure of the main system, each of said left and right processor units comprising a memory and a dual control unit for controlling which one of said left and right processor units is to be operated as the main system according to information obtained through the monitoring of the operating states of said left and right processor units;

wherein

said left processor unit further comprising means for generating a signal WRI_L to cause data in said memory of said left processor unit to be written into a first-in-first-out memory of an equalizing means according to a write operation when said left processor unit is in operation, and to cause data stored in said first-in-first-out memory to be read out and shifted to said left processor unit when said left processor unit is on standby;

said right processor unit further comprising means for generating a signal WRI_R to cause data in said memory of said right processor unit to be written into said first-in-first-out memory according to a write operation when said right processor unit is in operation, and to cause data stored in said first-in-first-out memory to be read out and shifted to said right processor unit when said right processor unit is on standby;

said left processor unit further comprising means for generating a control declaration signal CTL_L when said left processor unit is to be in operation;

said right processor unit further comprising means for generating a control declaration signal CTL_R when said right processor unit is to be in operation;

means for generating a dual control signal DCS_L to cause said left processor unit to be operated;

means for generating a dual control signal DCS_R to cause said right processor unit to be operated;

said dual control means comprises said equalizing means for continuously equalizing the contents of said memory in each of said left and right processor units, said equalizing means comprising said first-in-first-out memory;

means for controlling the shift-in SI of data to said first-in-first-out memory only when the following expression is satisfied;

space="preserve" listing-type="equation">SI=ACC.sub.L ·

WRI.sub.L ·

CTL.sub.L ·

DCS.sub.L +ACC.sub.R ·

WRI.sub.R ·

CTL.sub.R ·

DCS.sub.R ;

means for controlling the shift out SO of data from said first-in-first-out memory only when the following expression is satisfied;

space="preserve" listing-type="equation">SO=ACC.sub.L ·

WRI.sub.L ·

CTL.sub.L +ACC.sub.R ·

WRI.sub.R ·

CTL.sub.R

wherein ACC_L (or ACC_R) is a signal which becomes active in case of write-access or read-access from the left (or right) side processor unit to said first-in-first-out memory; and

means for monitoring the operational states of each of said left and right processor units and in response thereto for inhibiting access to said first-in-first-out memory when it is found that the above two expressions are not satisfied

so that data is protected from undesired loss and continuity of control is maintained at all times including the time that transfer of control between the left and right processor units occurs.

2. The system of claim 1, wherein said dual control unit comprises

two independent interruption means for indicating switching of said two processor units to the main system and to the subsidiary system;

a processor for generating an interrupt signal; and

an internal bus;

wherein

said two interruption means receive said interrupt signal from said processor through said internal bus, retain said interrupt signal according to a dual switching signal, and perform interruption for selective switching of said two processor units.

3. The system of claim 1, wherein said dual control unit further comprises interruption control means for generating interrupt signals FINT_L, FINT_R indicating interruption for a hierarchy of data reading priority to the two processor units according to the below expressions:

space="preserve" listing-type="equation">FINT.sub.L =ACC.sub.R ·

SI·

HFUL·

IF.sub.L +ACC.sub.L ·

FIN.sub.L +IRST·

FIN.sub.L

space="preserve" listing-type="equation">FIN.sub.L =FINT.sub.L

space="preserve" listing-type="equation">FINT.sub.R =ACC.sub.L ·

SI·

HFUL·

IF.sub.R +ACC.sub.R ·

FIN.sub.R +IRST·

FIN.sub.R

space="preserve" listing-type="equation">FIN.sub.R =FINT.sub.R

space="preserve" listing-type="equation">IF.sub.L =(FIN.sub.L ·

IF.sub.L +SO·

ACC.sub.L ·

EMPY)

space="preserve" listing-type="equation">IF.sub.R =(FIN.sub.R ·

IF.sub.R +SO·

ACC.sub.R ·

EMPY)

wherein, ACC denotes an access signal to the interruption control means;

subscript L indicates signals from the left processor unit and R indicates signals from the right processor unit;

SO denotes a shift-out signal from the first-in-first-out memory;

SI denotes a shift-in signal from the first-in-first-out memory;

HFUL denotes a half full signal generated when half of the data of the volume is loaded in the first-in-first-out memory;

EMPY denotes an empty signal generated when the first-in-first-out memory becomes empty;

FINT_L denotes an interrupt signal provided to the left processor unit;

FINT_R denotes an interrupt signal provided to the right processor unit;

IRST denotes a reset signal of the interrupt signals FINT_L, FINT_R provided from the left or right processor unit when the access signal is asserted.

4. The system of claim 1, wherein said two processor units comprise

mark insertion means for inserting a start mark and an end mark in each of said two processor units at points in time whereat actual operation of said each processor unit starts and ends;

end mark detection means for detecting the end mark from within data read out from said first-in-first-out memory; and

data loading means for loading data from said start mark to said end mark in an address when said end mark is detected;

wherein

a control signal for determining which processor unit is operated is transferred from data in which said start mark is inserted to a selected processor unit to start operation thereof.

5. The system of claim 1, further comprising

two supply means for feeding an operating power to each of said two processor units;

an input/output unit controlled by said two processor units;

a first bus connecting said two processor units and transmitting data for equalizing data bases mutually;

a second bus connecting each of said two processor units and said input/output unit for exchanging data with each other; and

wherein said two processor units each comprises bus function stop means for stopping at least the data transmission function of said first bus at time of ON and OFF operations of corresponding supply means and in an output voltage transient state.

6. The system of claim 5, wherein said bus function stop means comprises an open collector gate to which are applied a bus control signal and a signal coming to high level when a power voltage of one or more of said two supply means reaches an operable voltage.

7. The system of claim 1, further comprising

an input/output unit connected to said two processor units through an input/output bus;

means for providing a ready signal flag for indicating normalcy of operation thereof;

means for providing a capability signal flag indicating capability of being in operation; and

arithmetic operation output means for receiving a ready signal flag and a capability signal flag from said respective two means for providing, computing a logical product of both said signal flags, and transferring said operation output signal to said input/output unit;

said input/output unit deciding whether or not it is accessed according to said operation output signal from said arithmetic operation output means.

8. The system of claim 1, further comprising

a first bus connecting the dual control unit and each of said two processor units and transmitting data for equalizing a data base mutually;

a second bus connecting with said first bus through an intrastation communication unit functioning as an interface;

a plurality of input/output units;

a third bus; and

a nest common unit functioning as a bus repeater provided against said third bus to which said second bus and said plurality of input/output units are connected;

wherein said nest common unit comprises

comparison means for comparing a signal on said second bus and a signal on said third bus and for providing a mismatch signal when a mismatch is determined;

handshake means for exchanging a signal on said second bus and a signal on said third bus;

a flip-flop set on said mismatch signal from said comparison means;

a buffer for transmitting a signal from said flip-flop; and

said two processor units reading the contents of said flip-flop through said second bus by way of said buffer.