Semiconductor memory device and the manufacturing method thereof
First Claim
1. A semiconductor memory device including a first memory cell comprising:
- a semiconductor substrate;
a first conductive layer formed on said substrate;
a first and second access transistor each having a gate formed from said first conductive layer;
an insulating layer formed on said first and second access transistor gates, said insulating layer having a first and second contact hole therein to expose said first and second access transistor gates, respectively;
a second conductive layer formed on said insulating layer; and
a first and second word line formed from said second conductive layer, said first word line being connected to said first access transistor gate through said first contact hole, and said second word line being connected to said second access transistor gate through said second contact hole.
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Accused Products
Abstract
An SRAM memory cell structure is provided which has the access transistor gates formed from a different layer than that of the word line. The first access transistor gate of a first memory cell is connected to the first access transistor gate of an adjacent second memory cell, and a second access transistor gate of the first memory cell is connected to a second access transistor gate of an third oppositely adjacent memory cell. Each pair of coupled gates are formed separate from the access transistor gates in adjacent memory cells. The word lines connect the separated access transistor gates. The word lines are formed on an insulating layer above the gates of the access transistors. The word lines are, however, electrically connected to the gates of the access transistors through contact holes formed in the insulating layer. Each memory cell is arranged symmetrically with respect to an adjacent memory cell, and the components of each memory cell are symmetrical. Therefore, a structure and a method for a reduction in the area of an SRAM cell of the conventional circuit design is provided, resulting in a larger layout margin and a more reliable and more highly integrated SRAM device.
20 Citations
14 Claims
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1. A semiconductor memory device including a first memory cell comprising:
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a semiconductor substrate; a first conductive layer formed on said substrate; a first and second access transistor each having a gate formed from said first conductive layer; an insulating layer formed on said first and second access transistor gates, said insulating layer having a first and second contact hole therein to expose said first and second access transistor gates, respectively; a second conductive layer formed on said insulating layer; and a first and second word line formed from said second conductive layer, said first word line being connected to said first access transistor gate through said first contact hole, and said second word line being connected to said second access transistor gate through said second contact hole. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification