Semiconductor memory

• US 5,448,520 A
• Filed: 09/15/1994
• Issued: 09/05/1995
• Est. Priority Date: 05/13/1981
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Ikuzaki, Kunihiko, Kawamoto, Hiroshi, Shimohigashi, Katsuhiro, Masuda, Hiroo
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/306,612
• Time in Patent Office: 355 Days
• Field of Search: 365/154, 365/189.01, 365/189.03, 365/203, 365/207
• US Class Current: 365/189.15
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed irk the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Claims

1. A semiconductor memory comprising:

a pair of data lines which are formed substantially in parallel to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said data lines of said pair of data lines;

a plurality of dynamic memory cells, each of which is coupled to one of said word lines and to one of said data lines;

an amplifier, coupled to said pair of data lines, adapted to amplify a potential difference between said data lines so as to provide said data lines with a high-level potential and a low-level potential, respectively, wherein said amplifier includes a pair of N-channel MOS transistors and a pair of P-channel MOS transistors, wherein each transistor of said pair of N-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of N-channel MOS transistors, wherein a drain of one of said pair of N-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of N-channel MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of P-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of P-channel MOS transistors, and wherein a drain of one of said pair of P-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of P-channel MOS transistors is coupled to the other of said pair of data lines; and

a precharging circuit adapted to set said data lines at a predetermined level when said plurality of dynamic memory cells are in a non-selected state, wherein said predetermined level is an intermediate level between said high-level potential and said low-level potential.

2. A semiconductor memory according to claim 1, further comprising:

a first switching MOS transistor of N-channel type having a drain coupled to a source of each of said pair of N-channel MOS transistors and a source coupled to a first potential terminal; and

a second switching MOS transistor of P-channel type having a drain coupled to a source of each of said pair of P-channel MOS transistors and a source coupled to a second potential terminal.

3. A semiconductor memory according to claim 2,

wherein said precharging circuit includes a third switching MOS transistor having a source-drain path provided between said pair of data lines, and

wherein said third switching MOS transistor is controlled so that said pair of data lines are electrically coupled to each other when said plurality of dynamic memory cells are in said non-selected state.

4. A semiconductor memory according to claim 3,

wherein said first potential terminal has a potential level corresponding to said low-level potential, and

wherein said second potential terminal has a potential level corresponding to said high-level potential.

5. A semiconductor memory according to claim 4, further comprising a control circuit adapted to supply control signals to a gate of said first switching MOS transistor and a gate of said second switching MOS transistor, respectively, so that operation of said pair of N-channel MOS transistors is started at a time different from the time when operation of said pair of P-channel MOS transistors is started.

6. A semiconductor memory according to claim 4, further comprising a fourth switching MOS transistor of N-channel type having a drain coupled to said source of each of said pair of N-channel MOS transistors and a source coupled to said first potential terminal, wherein said fourth switching MOS transistor is turned "on" at a time different from the time when said first switching MOS transistor is turned "on".