Adaptive block size image compression method and system

• US 5,452,104 A
• Filed: 08/04/1993
• Issued: 09/19/1995
• Est. Priority Date: 02/27/1990
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lee, Chong U.
• Primary Examiner(s): Coles, Sr., Edward L.
• Assistant Examiner(s): VU, KIM Y
• Application Number:
  US08/102,124
• Time in Patent Office: 776 Days
• Field of Search: 358/261.1, 358/261.2, 358/261.3, 358/426, 358/427, 358/432, 358/433, 348/403, 348/404, 348/405, 382/41, 382/43, 382/56
• US Class Current: 358/426.14
• CPC Class Codes: G06T 9/40 Tree coding, e.g. quadtree, octree
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/102 characterised by the element, parameter or selection affected or controlled by the adaptive coding
• CPC Class Codes: H04N 19/129 Scanning of coding units, e.g. zig-zag scan of transform coefficients or flexible macroblock ordering [FMO]
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/146 Data rate or code amount at the encoder output
• CPC Class Codes: H04N 19/15 by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
• CPC Class Codes: H04N 19/154 Measured or subjectively estimated visual quality after decoding, e.g. measurement of distortion use of rate-distortion criteria H04N19/147
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/18 the unit being a set of transform coefficients
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/63 using sub-band based transform, e.g. wavelets
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
• CPC Class Codes: H04N 19/96 Tree coding, e.g. quad-tree coding
• CPC Class Codes: H04N 19/98 Adaptive-dynamic-range coding [ADRC]

Abstract

In an adaptive block size image compression method and system for compressing image data, a respective method and system for further compressing the image data for transmission. Each block and corresponding sub-blocks of pixel data is subjected to a discrete cosine transform (DCT) operation. Varying levels of sub-blocks of resulting corresponding transform coefficients are selected for construction into a composite transform coefficient block corresponding to each input block of pixel data. The selection of transform coefficient block size for the composite block is determined by a comparison process between transform block and sub-block coding efficiency. The composite block is variable length coded to further reduce bit count in the compressed data. A discrete quadtree transform (DQT) operation is in supplement of the adaptive block size block selection with coefficient replacement to optimize image data compression.

Claims

1. In an adaptive block size image compression system for compressing a block of input pixel data for transmission by performing a discrete cosine transform (DCT) operation on the block of pixel data and on at least one predetermined level of constituent sub-blocks thereof so as to produce corresponding image block and sub-blocks of DC and AC DCT coefficient values;

determining for each image block and each corresponding group of image sub-blocks of DCT coefficient values a bit count corresponding to the number of bits required to respectively encode the image block and each corresponding group of image sub-blocks of DCT coefficient values according to a predetermined coding format;

determining from the bit count ones of the image block and corresponding group of image sub-blocks of DCT coefficient values requiring a lesser number of bits to encode according to the coding format;

selecting ones of the image block and image sub-blocks of DCT coefficients values requiring a lesser number of bits to encode according to the coding format so as to form a composite image block;

ordering the DCT coefficient values of the composite image block according to a predetermined ordering format;

encoding the ordered DCT coefficient values of the composite image block according to the encoding format; and

assembling the encoded ordered DCT coefficient values of the composite image block along with information identifying the selected ones of the image block and image sub-blocks of DCT coefficient values of the composite image block, a subsystem for providing further compression of the block of pixel data comprising;

discrete quadtree transform means for, receiving said input block of pixel data, performing a first discrete cosine transform (DCT) operation on said block of pixel data so as to produce a corresponding first block of DC and AC DCT coefficient values, performing a series of additional DCT operations with a first additional DCT operation performed on said DC DCT coefficients of said first block of DC and AC DCT coefficient values with each subsequent additional DCT operation performed on resultant DC coefficients values of a proceeding additional DCT operation with a last additional DC operation producing a corresponding last block of DC and AC DCT coefficient values, and providing an output of said last block of DC and AC DCT coefficient values;

code length determination means for, receiving each of said last block of DC and AC DCT coefficient values, generating a corresponding code length value corresponding to a length of each of said last block DC and AC DCT coefficient value as encoded according to said predetermined coding format, inserting each code length value in place of a DC DCT coefficient for each corresponding image block and image sub-block in said bit count determination, wherein said ones of said image block and image sub-blocks are selected for said composite image block using said corresponding code length values; and

replacement means for receiving each of said last block of DC and AC DCT coefficient values and replacing each DC DCT coefficient of said selected ones of said image block and image sub-blocks of said composite image block with a corresponding one of said last block DC and AC DCT coefficient values.

2. The subsystem of claim 1 wherein said replacement means further comprises:

ordering means for ordering said last block DC and AC DCT coefficient values according to said predetermined ordering format; and

encoder means for encoding each of said last block DC and AC DCT coefficient values according to said predetermined encoding format.

3. In an adaptive block size compression system wherein a block of pixel data is transformed to AC and DC discrete cosine transform (DCT) coefficient data for a block and constituent sub-blocks of pixel data, and wherein the AC and DC DCT coefficient values of a composite block of selected ones of said block and constituent sub-blocks of pixel data are provided for transmission, an apparatus for compressing said DC DCT coefficient values comprising:

discrete quadtree means for receiving at least one block of data representing said block of pixel data, performing a plurality of DCT operations to provide AC and DC DQT coefficient values, with a first DCT operation performed on said at least one block of data to provide first sub-blocks of AC and DC DQT coefficient values, performing at least one additional DCT operation wherein each of said at least one additional DCT operation is performed on resultant DC DQT coefficient data of a preceding DCT operation, and selecting ones of AC and DC DQT coefficient values to provide a DQT composite block of AC and DC coefficient values; and

encoding means for receiving said DQT composite block, selecting values from said DQT composite block and encoding said selected values of said DQT composite block to provide a signal indicative of compressed DC DCT coefficient values.

4. The apparatus of claim 3 wherein said discrete quadtree means comprises:

at least one DCT means for receiving said at least one block of data and performing a series of DCT operations to provide AC and DC DQT coefficient values with a first DCT operation performed on said at least one block of data and with additional DCT operations performed on sub-blocks of selected DC DQT coefficient values; and

selector means for receiving said AC and DC DQT coefficient values selecting ones of said AC and DC DQT, coefficient values to provide said sub-blocks of selected DC DQT coefficient values in accordance with a predetermined selection format.

5. The apparatus of claim 4 wherein said at least one DCT means comprises a plurality of single DCT means wherein each of said single DCT means is for performing a corresponding one of said series of DCT operations.

6. The apparatus of claim 5 wherein said selector means further comprises:

at least one multiplexer means for receiving AC and DC DQT coefficient values from a corresponding one of said at least one single DCT means and selecting ones of said AC and DC DQT coefficient values to provide intermediate DQT composite blocks of AC and DC DQT coefficient values; and

at least one single selector means for receiving said intermediate DQT composite blocks, selecting values from said intermediate DQT composite blocks to provide said sub-blocks of selected DC DQT coefficient values.

7. The apparatus of claim 3 wherein said at least one block of data comprises pixel data.

8. The apparatus of claim 3 wherein said at least one block of data comprises said sub-blocks of AC and DC DCT coefficient values.

9. The apparatus of claim 6 wherein said encoding means is responsive to a selection signal.

10. The apparatus of claim 9 wherein said encoding means comprises a replacement means for receiving said DQT composite block of AC and DC DQT coefficient values and said selection signal and replacing selected values of said composite block of AC and DC DQT coefficient values with a predetermined dummy value in accordance with said selection signal to provide a value replaced composite block.

11. The apparatus of claim 10 wherein said encoding means further comprises:

zig-zag scan serializer means for receiving said value replaced composite block and reordering the members of said value replaced composite block to provide a reordered composite block; and

value removal logic means for removing selected values from said reordered composite block in accordance with a predetermined removal format to provide a compressed composite block.

12. The apparatus of claim 11 further comprising quantization means for receiving said compressed composite block and quantizing values of said compressed composite block in accordance with a predetermined quantization format.

13. In an adaptive block size compression system wherein a block of pixel data is transformed to AC and DC discrete cosine transform (DCT) coefficient data for a block and at least one constituent level of sub-blocks of pixel data, and wherein the AC and DC DCT coefficient values of a composite block of selected ones of said block and constituent sub-blocks of pixel data are provided for transmission, a method for compressing said DC DCT coefficient values comprising:

receiving at least one block of data;

performing a series of discrete cosine transformation (DCT) operations to provide AC and DC DQT coefficient values with a first DCT operation performed on said at least one block of data to provide first sub-blocks of AC and DC DQT coefficient values and at least one additional DCT operations is performed on sub-blocks of selected DC DQT coefficient values resultant from a preceding DCT operation of said series of DCT operations; and

selecting ones of AC and DC DQT coefficient values resultant from said first DCT operation and said at least one additional DCT operation to provide a DQT composite block of AC and DC DQT coefficient values.

14. The method of claim 13 further comprising the steps of:

receiving a selection signal;

replacing values of said DQT composite block of selected values with a predetermined dummy element in accordance with said selection signal to provide a value replaced composite block.

15. The method of claim 14 further comprising the steps of:

reordering the elements of said value replaced composite block in accordance with a predetermined zig zag format to provide a reordered composite block; and

removing selected elements of said reordered composite block in accordance with said selection signal to provide a value removed composite block.

16. The method of claim 15 further comprising the step of quantizing the values of said value removed composite block to provide quantized values.

17. The method of claim 16 further comprising the step of encoding said quantized values in accordance with a predetermined coding format.

18. An image compression apparatus for compressing data representative of a block of pixel data comprising:

transform means for receiving an input block of pixel data and performing a discrete cosine transform (DCT) operation on said block of pixel data and on at least one predetermined level of constituent sub-blocks of pixel data thereof to provide corresponding AC and DC DCT coefficient values for said block and constituent sub-blocks and selecting ones of said AC and DC DCT coefficient values to provide a composite block of AC and DC DCT coefficient values representing said input block of pixel data;

DC DCT compression means for compressing the DC DCT values of said composite block of AC and DC DCT coefficient values by performing a series of DCT operations to provide AC and DC DQT coefficient values, with a first DCT operation performed on sub-blocks of said DC DQT values of said constituent sub-blocks of pixel data and additional DCT operations performed on sub-blocks of DC DQT values from preceding DCT operations of said series of DCT operations and encoding ones of said AC and DC DQT coefficient values to provide compressed DC DCT coefficient values; and

combination means for receiving said composite block of AC and DC DCT and said compressed DC DCT coefficient values and combining said composite block of AC and DC DCT and said compressed DC DCT coefficient values to provide a composite block of AC and compressed DC DCT coefficient values.

19. The apparatus of claim 18 wherein said DC DCT compression means comprises:

discrete quadtree means for performing said series of DCT operations on said sub-blocks of DC DQT coefficient values to provide said AC and DC DQT coefficient values, with said first DCT operation performed on said sub-blocks of DC DQT coefficient values of said constituent sub-blocks of pixel data and said additional DCT operations performed on said sub-blocks of DC DQT values from preceding said DCT operations of said series of DCT operations, and selecting ones of said AC and DC DQT coefficient values to provide said DQT composite block; and

encoding means for receiving said DQT composite block, selecting values from said DQT composite block and encoding said selected values of said DQT composite block to provide said compressed DC DCT coefficient values.

20. The apparatus of claim 19 wherein said discrete quadtree means comprises:

at least one DCT means for performing said series of DCT operations on said sub-blocks of DC DQT coefficient values to provide said AC and DC DQT coefficient values, with said first DCT operation performed on said sub-blocks of DC DQT coefficient values of said constituent sub-blocks of pixel data and said additional DCT operations performed on said sub-blocks of DC DQT values from said preceding DCT operations of said series of DCT operations, and selecting ones of said AC and DC DQT coefficient values to provide said DQT composite block; and

selector means for receiving said AC and DC DQT coefficient values selecting said ones of said AC and DC DQT coefficient values to provide said sub-blocks of DC DQT values.

21. The apparatus of claim 20 wherein said at least one DCT means comprises a plurality of single DCT means wherein each of said single DCT means is for performing a corresponding one of said series of DCT operations.

22. The apparatus of claim 21 wherein said selector means further comprises:

at least one multiplexer means for receiving AC and DC DQT coefficient values from a corresponding one of said at least one single DCT means and selecting ones of said AC and DC DQT coefficient values to provide intermediate DQT composite blocks of AC and DC coefficient values; and

at least one single selector means for receiving said intermediate DQT composite blocks, selecting values from said intermediate DQT composite blocks to provide said sub-blocks of selected DC DQT coefficient values.

23. The apparatus of claim 22 further comprising:

DC code length means for receiving said compressed DC DCT coefficient values and providing a DC code length indicative of the number of bits to encode said DC DCT coefficient data of said blocks and sub-blocks of pixel data;

AC code length means for receiving said blocks and sub-blocks of AC and DC DCT coefficient values and providing an AC code length indicative of the number of bits to encode said AC DCT coefficient data of said blocks and sub-blocks of pixel data; and

block selection means for receiving said DC code length and said AC code length and providing a selection signal indicative of said selected ones of said block and sub-blocks of AC and compressed DC DCT coefficient values of said composite block of AC and compressed DC DCT coefficient values in accordance with a weighted sum of said AC code length and said DC code length.

24. The apparatus of claim 23 wherein said encoding means is responsive to said selection signal.

25. The apparatus of claim 24 wherein said encoding means comprises replacement means for receiving said DQT composite block and said selection signal and replacing selected values of said DQT composite block with a predetermined dummy value to provide a value replaced composite block.

26. The apparatus of claim 25 wherein said encoding means further comprises:

zig-zag scan serializer means for receiving said value replaced composite block and reordering values of said value replaced composite block to provide a reordered composite block; and

value removal logic means for receiving said reordered composite block and removing selected values from said reordered composite block in accordance said selection signal to provide a value removed composite block.

27. The apparatus of claim 26 further comprising quantization means for receiving said value removed composite block and quantizing values of said value removed composite block in accordance with a predetermined quantization format a quantized DC value composite block.

28. A method for compressing image data for a block of pixel data comprising the steps of:

receiving an input block of pixel data;

performing a discrete cosine transform (DCT) operation on said block of pixel data and on at least one predetermined level of constituent sub-blocks of pixel data thereof to provide corresponding AC and DC DCT coefficient values for said block and constituent sub-blocks;

selecting ones of said AC and DC DCT coefficient values to provide a composite block of AC and DC DCT coefficient values representing said input block of pixel data;

performing a series of DCT operations on said DC DCT coefficient values for said constituent sub-blocks to provide AC and DC DQT coefficient values, with a first DCT operation performed on said DC DCT values of said constituent sub-blocks of pixel data and additional DCT operations performed on sub-blocks of DC DQT values from preceding DCT operations of said series of DCT operations;

encoding ones of said AC and DC DQT coefficient values to provide compressed DC DCT coefficient values; and

combining said composite block of AC and DC DCT and said compressed DC DCT coefficient values to provide a composite block of AC and compressed DC DCT coefficient values.

29. The method of claim 28 further comprising the steps of:

providing a DC code length indicative of the number of bits to encode said DC DCT coefficient data of said blocks and sub-blocks of pixel data;

providing an AC code length indicative of the number of bits to encode said AC DCT coefficient data of said blocks and sub-blocks of pixel data; and

providing a selection signal in accordance with a weighted sum of said AC code length and DC code length.

30. The apparatus of claim 29 wherein said step of encoding is responsive to said selection signal.

31. The method of claim 30 wherein said step of step of encoding comprises:

replacing selected ones of said AC and DC DQT coefficient values with a predetermined dummy value to provide a value removed composite block;

reordering the members of said value removed composite block in accordance with a predetermined zig zag format to provide a reordered composite block; and

removing selected values from said reordered composite block in accordance with a predetermined value removal format to provide a value removed composite block.

32. The method of claim 31 further comprising quantizing the values of said value removed composite block in accordance with a predetermined quantization format to provide compressed DC values.

33. In an image decoder wherein an image block of pixel data is processed by performing a discrete cosine transform (DCT) operation on said block of pixel data and on at least one predetermined level of constituent sub-blocks of pixel data thereof to provide corresponding block and sub-blocks of AC and DC DCT coefficient values, and wherein said DC DCT coefficient values are compressed by performing a series of DCT operations performed on said DC DCT coefficient values of said sub-blocks of pixel data to provide AC and DC DQT coefficient values with a first of said series of DCT operations performed on said sub-blocks of DC DCT coefficient values with at least one additional DCT of said series of additional DCT operations performed on selected sub-blocks of said DC DCT coefficient values and said DC DQT of previous DCT operations of said series of DCT operations to provide a composite block of AC and DC DQT coefficient values, and wherein selected values of said composite block of AC and DC DQT coefficient values are encoded to provide compressed DC DCT coefficient values, and wherein a signal is provided indicative of said compressed DC DCT coefficient values and selected ones of said block and sub-blocks of AC and DC DCT coefficient values, an apparatus for decoding said compressed DC DCT coefficient values comprising:

separator means for receiving said signal indicative of said compressed DC DCT coefficient values and selected AC DCT values of said block and sub-blocks of AC and DC DCT coefficient values and providing a signal indicative of said compressed DC DCT coefficient values in accordance with a predetermined separation format;

decoder means for receiving said signal indicative of said compressed DC DCT coefficient values and providing said decoded DC DCT coefficient values in accordance with a predetermined decoding format; and

inverse discrete quadtree means for receiving said decoded DC DCT coefficient values, performing a series of inverse discrete cosine transformation (IDCT) operations to provide AC and DC IDCT coefficient values with a first IDCT performed on selected values of said processed DC DCT coefficient values and additional IDCT operations performed on additional selected values of said processed DC DCT coefficient values and resultant AC and DC IDCT values from preceding IDCT operations and wherein ones of said AC and DC IDCT coefficient values are provided as said DC DCT coefficient values.

34. The apparatus of claim 33 wherein said decoder means comprises:

lookup table means for receiving said signal indicative of said compressed DC DCT coefficient values, providing a composite block of quantized processed DC DCT coefficient values in accordance with a predetermined lookup format; and

inverse quantizer means for receiving said composite block of quantized processed DC DCT coefficient values and providing said decoded DC DCT coefficient values in accordance with a predetermined inverse quantization format.

35. The apparatus of claim 34 wherein said decoder means further comprises an expansion means disposed between lookup table means and said inverse quantizer means for receiving said composite block of quantized processed DC DCT coefficient values and inserting a predetermined dummy value in said composite block of quantized processed DC DCT coefficient values and reordering said resulting values in accordance with an inverse zig zag format.

36. The apparatus of claim 35 wherein said expansion means is responsive to a block size assignment signal.

37. The apparatus of claim 36 wherein said inverse discrete quadtree means comprises:

selector means for receiving said decoded DC DCT coefficient values and resultant AC and DC IDCT values from previous IDCT operations, and providing sub-blocks of selected decoded DC DCT coefficient values and resultant AC and DC IDCT values in accordance with a predetermined selection format; and

at least one inverse discrete cosine means for receiving said selected sub-blocks and performing an IDCT operation of said series IDCT operations on said sub-blocks of selected decoded DC DCT coefficient values and resultant AC and DC IDCT values.

38. The apparatus of claim 37 wherein said at least one IDCT means comprises a plurality of single IDCT means wherein each of said single IDCT means is for performing a corresponding one of said series of IDCT operations.

39. The apparatus of claim 38 wherein said selector means comprises:

plurality of separator means with a first separator means for receiving said decoded DC DCT coefficient values, providing a block of DCT coefficient values to a corresponding single IDCT means and separately providing remaining AC and DC DCT coefficient values to a corresponding multiplexer means and additional separator means for receiving a corresponding intermediate composite block of IDCT coefficient values and separating sub-blocks of AC and DC IDCT coefficient values from remaining AC and DC DCT coefficient values; and

plurality of multiplexer means each of said multiplexer means for receiving resultant AC and DC IDCT coefficient values from a corresponding single IDCT means and said remaining AC and DC DCT coefficient values to provide an intermediate composite block of IDCT coefficient values.

40. In an image decoder wherein an image block of pixel data is processed by performing a discrete cosine transform (DCT) operation on said block of pixel data and on at least one predetermined level of constituent sub-blocks of pixel data thereof to provide corresponding block and sub-blocks of AC and DC DCT coefficient values, and wherein said DC DCT coefficient values are compressed by performing a series of DCT operations performed on said DC DCT coefficient values of said sub-blocks of pixel data to provide AC and DC DQT coefficient values with a first of said series of DCT operations performed on said sub-blocks of DC DCT coefficient values with at least one additional DCT of said series of additional DCT operations performed on selected sub-blocks of said DC DCT coefficient values and said DC DQT coefficient values of previous DCT operations of said series of DCT operations to provide a composite block of AC and DC DQT coefficient values, and wherein selected values of said composite block of AC and DC DQT coefficient values are encoded to provide compressed DC DCT coefficient values, and wherein a signal is provided indicative of said compressed DC DCT coefficient values and selected ones of said block and sub-blocks of AC and DC DCT coefficient values, a method for decoding said compressed DC DCT coefficient values comprising the steps of:

receiving said signal indicative of a composite block of AC and compressed DC coefficient values;

providing compressed DC coefficient values from said composite block of AC and compressed DC coefficient values in accordance with a predetermined separation format;

decoding compressed DC coefficient values accordance with a predetermined decoding format to provide decoded DC DCT coefficient values; and

performing a series of inverse discrete cosine transformation (IDCT) operations to provide AC and DC IDCT coefficient values with a first IDCT performed on blocks of selected values of said compressed DC DCT coefficient values and additional IDCT operations performed on additional selected values of said compressed DC DCT coefficient values and resultant AC and DC IDCT values from preceding IDCT operations of said series of IDCT operations.

41. The apparatus of claim 40 wherein said step of decoding comprises the steps of comprises:

receiving said signal indicative of said compressed DC DCT coefficient values;

providing a composite block of quantized processed DC DCT coefficient values in accordance with a predetermined lookup format; and

inverse quantizing said processed DC DCT coefficient values in accordance with a predetermined inverse quantization format to provide said decoded DC DCT coefficient values.

42. The apparatus of claim 41 wherein said step of decoding further comprises the steps of:

inserting a predetermined dummy value in said composite block of quantized processed DC DCT coefficient values to provide a value inserted composite block; and

reordering said value inserted composite block in accordance with a inverse zig zag format.

43. The apparatus of claim 42 wherein said step of decoding is responsive to a block size assignment signal.

44. In an image decoder wherein an image block of pixel data is processed by performing a discrete cosine transform (DCT) operation on said block of pixel data and on at least one predetermined level of constituent sub-blocks of pixel data thereof to provide corresponding block and sub-blocks of AC and DC DCT coefficient values, performing a series of additional DCT operations on said sub-blocks of DC DCT coefficient values with additional DCT operations performed on selected sub-blocks of said DC DCT coefficient values and resultant DC DCT of previous DCT operations of said series of DCT operations to provide a composite block of AC and DC DQT coefficient values, encoding selected values of said composite block of AC and DC DQT coefficient values to provide compressed DC DCT coefficient values and combing selected ones of said block and sub-blocks of AC and DC DCT coefficient values and said compressed DC DCT coefficient values to provide a signal indicative of a compressed block of AC and compressed DC coefficient values, an apparatus for decoding said processed DC DCT coefficient values comprising:

separator means for receiving said signal indicative of a composite block of AC and compressed DC coefficient values and separating a signal indicative of said processed DC DCT coefficient values from said signal indicative of a compressed block of AC and compressed DC coefficient values in accordance with a predetermined separation format;

decoder means for receiving said signal indicative of said processed DC DCT coefficient values and providing said processed DC DCT coefficient values in accordance with a predetermined decoding format;

inverse discrete quadtree means for receiving said processed DC DCT coefficient values, performing a series of inverse discrete cosine transformation (IDCT) operations to provide AC and DC IDCT coefficient values with a first IDCT performed on selected values of said processed DC DCT coefficient values and additional IDCT operations performed on additional selected values of said processed DC DCT coefficient values and resultant AC and DC IDCT values from preceding IDCT operations;

combination means for receiving said AC DCT coefficient values and said DC IDCT coefficient values to provide a composite block of AC and decoded DC coefficient values and

inverse transform for performing at least one IDCT operation on said composite block of AC and decoded DC coefficient values to provide a composite pixel block.

45. The apparatus of claim 44 wherein said decoder means comprises:

lookup table means for receiving said signal indicative of said compressed DC DCT coefficient values providing a composite block of quantized processed DC DCT coefficient values in accordance with a predetermined lookup format; and

inverse quantizer means for receiving said composite block of quantized processed DC DCT coefficient values to provide said processed DC DCT coefficient values in accordance with a predetermined inverse quantization format.

46. The apparatus of claim 45 wherein said decoder means further comprises:

value insertion logic means for receiving said composite block of quantized processed DC DCT coefficient values for inserting a predetermined dummy value in said composite block of quantized processed DC DCT coefficient values to provide a value inserted composite block; and

reordering means for receiving said value inserted composite block reordering the values of said value inserted composite block in accordance with a predetermined inverse zig zag format.

47. The apparatus of claim 46 wherein said value insertion logic means and reordering means is responsive to a block size assignment signal.

48. The apparatus of claim 47 wherein said inverse discrete quadtree means comprises:

selector means for receiving said processed DC DCT coefficient values and said AC and DC IDCT coefficient values and providing blocks of selected ones said of processed DC DCT coefficient values and said AC and DC IDCT coefficient values in accordance with a predetermined selection format; and

at least one IDCT means for receiving said blocks of selected ones of processed DC DCT coefficient values and AC and DC IDCT coefficient values and performing a series of IDCT operations with each of said IDCT operations of said series of IDCT operations performed on blocks of said processed DC DCT coefficient values and resultant AC and DC IDCT values.

49. The apparatus of claim 48 wherein said at least one IDCT means comprises a plurality of single IDCT means wherein each of said single IDCT means is for performing a corresponding one IDCT operation of said series of inverse discrete cosine operation.

50. The apparatus of claim 49 wherein said selector means comprises:

plurality of separator means with a first separator means for receiving said processed DC DCT coefficient values providing a block of DCT coefficient values and separately providing remaining AC and DC DCT coefficient values with additional separator means for receiving a corresponding intermediate composite block of IDCT coefficient values and providing blocks of AC and DC IDCT coefficient values and separately providing additional remaining AC and DC IDCT coefficient values; and

plurality of multiplexer means each of said multiplexer means for receiving resultant AC and DC IDCT coefficient values from a corresponding single IDCT means and remaining AC and DC DCT coefficient values from a corresponding separator means to provide an intermediate composite block of IDCT coefficient values.

51. A method for decoding a block of pixel data wherein an image block of pixel data is processed by performing a discrete cosine transform (DCT) operation on said block of pixel data and on at least one predetermined level of constituent sub-blocks of pixel data thereof to provide corresponding block and sub-blocks of AC and DC DCT coefficient values, performing a series of additional DCT operations on said sub-blocks of DC DCT coefficient values with additional DCT operations performed on selected sub-blocks of said DC DCT coefficient values and resultant DC DCT of previous DCT operations of said series of DCT operations to provide a composite block of AC and DC DQT coefficient values, encoding selected values of said composite block of AC and DC DQT coefficient values to provide compressed DC DCT coefficient values and combining selected ones of said block and sub-blocks of AC and DC DCT coefficient values and said compressed DC DCT coefficient values to provide a signal indicative of a compressed block of AC and compressed DC coefficient values, a method for decoding said block of pixel data comprising the steps of:

receiving said signal indicative of a composite block of AC and compressed DC coefficient values;

providing said compressed DC coefficient values of said composite block of AC and compressed DC coefficient values;

separately providing said AC coefficient values of said composite block of AC and compressed DC coefficient values;

decoding said compressed DC DCT coefficient values in accordance with a predetermined decoding format to provide decoded DC DCT values;

performing a series of inverse discrete cosine transformation (IDCT) operations to provide AC and DC IDCT coefficient values with a first IDCT performed on blocks of selected values of said processed DC DCT coefficient values and additional IDCT operations performed on blocks of selected values of said processed DC DCT coefficient values and resultant AC and DC IDCT values from preceding IDCT operations wherein ones of said AC and DC IDCT values and decoded DCT values are provided as uncompressed DC DCT coefficient values; and

combining said AC DCT coefficient values and said uncompressed DC DCT coefficient values to provide a composite block of AC and uncompressed DC coefficient values; and

performing at least one IDCT operation on said composite block of AC and uncompressed DC coefficient values to provide a composite pixel block.

52. The method of claim 51 wherein said step of decoding comprises the steps of:

receiving said compressed DC DCT coefficient values;

providing a composite block of quantized processed DC DCT coefficient values in accordance with a predetermined lookup format; and

inverse quantizing said composite block of quantized processed DC DCT coefficient values.

53. The method of claim 52 wherein said step of decoding further comprises:

inserting a predetermined dummy value in said composite block of quantized processed DC DCT coefficient values to provide a value inserted composite block; and

reordering the values of said value inserted composite block in accordance with a predetermined inverse zig zag format.

54. The method of claim 53 wherein said steps of inserting said predetermined dummy value and reordering the values of said value inserted composite block are responsive to a block size assignment signal.

55. In an adaptive block size compression system wherein a block of pixel data is transformed to AC and DC discrete cosine transform (DCT) coefficient data for constituent blocks of vary block size, a sub-system for compressing said DC DCT coefficient data comprising:

discrete quadtree means having a first input for receiving at least one block of data and having an output wherein said discrete quadtree means comprises;

plurality of DCT means with a first DCT means having an input for receiving said at least one block of data and having an output with each additional DCT means having an input and an output; and

at least one selector means disposed between each of said plurality of DCT means having and input coupled to a corresponding DCT means output and output coupled to a corresponding one of said additional DCT means input; and

selection means having an input coupled to said discrete quadtree means output and having an output.

56. The apparatus of claim 55 wherein said at least one selector means has a second output and said discrete quadtree means further comprises at least one multiplexer means disposed between one of said additional DCT means and one of said at least one selector means having a first input coupled to said additional DCT means output and a second input coupled to said selector means second output and having an output coupled to said selector means input.

57. The apparatus of claim 56 wherein selection means comprises:

first selection multiplexer having a first input coupled to said DQT means, a second input for receiving a selection signal, a third input for receiving a dummy signal, and having an output; and

additional selection multiplexer means having a first input coupled to a corresponding selection multiplexer output, a second input for receiving a selection signal, a third input for receiving a dummy signal, and having an output.

58. The apparatus of claim 57 wherein said selection means further comprises:

zig zag scan serializer having an input coupled to a last selection multiplexer means of said additional selection multiplexer means output and having an output;

value removal logic means having an input coupled to said zig zag scan serializer output and having and output; and

code lookup table means having an input coupled to said value removal logic means output and having an output.

59. In an image decoder wherein and image block of pixel data is processed by performing a discrete cosine transform (DCT) operation on said block of pixel data and on at least one predetermined level of constituent sub-blocks of pixel data thereof, and providing corresponding block and sub-blocks of AC and DC DCT coefficient values and wherein said DC DCT coefficient values is further processed by performing a series of at least one additional DCT operation on said sub-blocks of DC DCT coefficient values, a subsystem for decoding said processed DC DCT coefficient values comprising:

decoder means having an input for receiving a signal indicative of said processed DC DCT coefficient values and having an output; and

inverse discrete quadtree means having an input coupled to said decoder means output, wherein said inverse discrete quadtree means comprises;

plurality of separator means with a first separator means having an input for receiving said signal indicative of said processed DC DCT coefficient values and additional separator means having an input and an output;

at least one inverse discrete means disposed between said plurality of separator means having an input coupled to a corresponding separator means output.

60. The apparatus of claim 59 wherein said separator means further having a second output and wherein said discrete quadtree means further comprises:

at least one multiplexer means having an input for receiving a timing signal, a second input coupled to a corresponding inverse cosine transform means output and a third input coupled to a corresponding second separator means output.

61. The apparatus of claim 60 wherein said decoder means comprises:

decode lookup table means having an input for receiving signal indicative of said processed DC DCT coefficient values and having an output;

value insertion logic means having a first input coupled to said decode lookup table means output, a second input for receiving a selection signal, and having an output;

inverse zig-zag scan insertion logic means having a first input coupled to said value insertion logic means output an a second input for receiving a selection signal, and having an output; and

inverse quantizer means having an input coupled to said inverse zig-zag scan insertion logic means output and having an output.