Serial address generator for burst memory

• US 5,452,261 A
• Filed: 06/24/1994
• Issued: 09/19/1995
• Est. Priority Date: 06/24/1994
• Status: Expired due to Term

• Current Assignee: Home Semiconductor Corporation (Home Semiconductor Corporation (Samoa))
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Chung, Jinyong, Murray, Michael A.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/265,535
• Time in Patent Office: 452 Days
• Field of Search: 365/230.01, 365/230.06, 365/230.08, 365/230.09, 365/236, 365/239, 365/240, 365/221, 365/233
• US Class Current: 365/233.11
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Abstract

A serial address generator for a sequential (burst mode) random access memory generates a sequence of internally generated addresses for fast cycling. The start address is externally provided. Then, as the clock signals arrive, the subsequent addresses are generated in sequence by the address sequencer. The address sequencer is preset to the second address in the sequence following the start address. Simultaneously, the start address is connected by an external address enable switch to an output terminal of the address generator, bypassing the address sequencer. When the first clock signal arrives at the address sequencer, the address sequencer output is sampled by closing an internal address enable switch and opening the external address enable switch. Thus the internally generated addresses are provided immediately following the start address. The address sequencer thereby generates each address one clock cycle ahead of that in the prior art, and the output address is provided one half clock cycle ahead of that in the prior art.

Claims

1. An address generator for a random access memory, comprising:

an address sequencer having a clock input terminal, a preset terminal, and an output terminal;

an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; and

an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator;

wherein the address sequencer includes means for incrementally timing the address sequencer to generate a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.

2. The address generator of claim 1, further comprising:

means for controlling the internal address enable switch; and

means for controlling the external address enable switch, wherein the means for controlling the external address enable switch closes the external address enable switch for a duration of the first address of the sequence of addresses, and

wherein during the duration the external address enable switch is closed, the address sequencer generates the second address in the sequence of addresses.

3. The address generator of claim 1, wherein the second address is output to the output terminal of the address sequencer only when the internal address enable switch is closed.

4. The address generator of claim 1, further comprising a buffer serially connected between the output terminal of the address sequencer and the output terminal of the address generator.

5. The address generator of claim 2, further comprising means for providing a preset signal of a predetermined duration and level to the preset terminal during at least a portion of the duration of the first address, the preset signal setting the address sequencer to the second address in the sequence of addresses.

6. The address generator of claim 2, further comprising means for providing clock signals of predetermined level to the clock input terminal, a first of the clock signals occurring only after the duration of the first address.

7. The address generator of claim 2, wherein the address sequencer includes a counter having a master portion and a slave portion.

8. The address generator of claim 1, further comprising means for providing an externally generated address to the address input terminal, wherein the externally generated address is a first address of a page of the random access memory.

11. The address generator of claim 2, wherein the means for controlling the internal address enable switch is a logical inversion of the signals provided to the clock input terminal.

9. An address generator for a random access memory, comprising:

means for providing a first address in a sequence of addresses, the first address being provided from an external source as an output address;

an address sequencer for generating the subsequent addresses in the sequence of addresses, a second address in the sequence being provided as an output address immediately following the generation of the first address;

an internal address enable switch connected between an output terminal of the address sequencer and an output terminal of the address generator;

an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and

means for incrementally timing the address sequencer during a preset period to generate the second address at a same time that the first address is being provided from the external source.

10. A method of generating a sequence of addresses for addressing a random access memory, comprising the steps of:

providing from an external source a first address in the sequence as an output address;

switching in the first address as an output address during a preset period;

then, providing from an address sequencer a second address in the sequence as an output address, the second address being generated by incremental timing during at least a part of a duration of the step of providing the first address; and

switching in the second address as an output address after the preset period.

12. An address generator for a random access memory, comprising:

an address sequencer having a clock input terminal, a preset terminal, and an output terminal;

an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator;

an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and

means for providing a preset signal of a predetermined duration and level to the preset terminal during at least a portion of the duration of the first address, the preset signal setting the address sequencer to the second address in the series;

wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.

13. An address generator for a random access memory, comprising:

an address sequencer having a clock input terminal, a preset terminal, and an output terminal;

an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator;

an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and

means for providing clock signals of predetermined level to the clock input terminal, a first of the clock signals occurring only after the duration of the first address;

wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.

14. An address generator for a random access memory, comprising:

an address sequencer having a clock input terminal, a preset terminal, and an output terminal;

an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; and

an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator;

wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch, and

wherein the address sequencer includes a counter having a master portion and a slave portion.