Image digitizer including pixel engine

• US 5,452,378 A
• Filed: 04/28/1994
• Issued: 09/19/1995
• Est. Priority Date: 12/13/1991
• Status: Expired due to Fees

• Current Assignee: Avid Technology Incorporated
• Original Assignee: Avid Technology Incorporated
• Inventors: Rosen, B. Joshua, Peters, Eric C.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Chang, Jon
• Application Number:
  US08/234,263
• Time in Patent Office: 509 Days
• Field of Search: 382/50, 382/58, 382/62, 382/63, 382/8, 358/443, 358/444, 358/445, 345/190, 395/163, 395/166
• US Class Current: 382/312
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 5/9264 using transform coding
• CPC Class Codes: H04N 9/64 Circuits for processing colour signals H04N9/77 takes precedence; camera processing pipelines for processing colour signals H04N23/84

Abstract

An image digitizer including a pixel engine connected to both a video memory and a processor. The pixel engine is configured to enable pixels to be transferred out of memory or read into memory while bypassing the processor thereby allowing more efficient transfer of data into and out of the image digitizer.

Claims

1. An image digitizer comprising:

video memory for storing digital pixel data;

a FIFO interface;

a processor having address space divided into a plurality of regions including a first region for identifying locations of pixels for being accessed by the processor for processing, and a second region for identifying locations of pixels to be transferred from the video memory to the FIFO interface;

a pixel engine intermediate the video memory and the processor so that data passing between the video memory and the processor through the pixel engine, wherein the pixel engine has means for enabling pixels to be transferred between the video memory and the FIFO interface while bypassing the processor, and, wherein, in response to an address to the first region, the pixel engine allows access from the processor to the video memory through the pixel engine.

2. The image digitizer of claim 1, further including a pixel expander/compressor connected to the FIFO interface.

3. The image digitizer of claim 1, wherein the address space of the processor includes a third region for accessing control functions and operating modes in the pixel engine.

4. The image digitizer of claim 1, wherein the processor is programmed to subsample pixels.

5. An image digitizer comprising:

a video memory for storing digital pixel data in memory locations;

a processor for processing pixel data;

an interface for storing data; and

a pixel engine connected between the video memory, the processor, and the interface, the pixel engine for transferring pixel data between the video memory and the interface;

wherein the processor has an address space divided into at least two blocks including

a first block for identifying pixels in a location in video memory for processing by the processor, and

a second block for identifying pixels in a location to be transferred between the video memory and the interface; and

wherein the pixel engine includes

means for determining whether a first or second block is being addressed by the processor,

means for connecting the processor to the video memory to allow the processor unimpeded access through the pixel engine to the pixels at the location in video memory in response to an address in the first block, and

means for transferring pixels between the video memory and the interface in response to an address in the second block, wherein the means for transferring transfers pixels independent of the processor.

6. The image digitizer of claim 5, wherein there is a plurality of pixels for each location in the video memory corresponding to a plurality of pixels, and wherein the pixel engine transfers the pixels in response to an address to the location in the second block.

7. The image digitizer of claim 6, wherein the processor has means for subsampling by selecting a group of locations at fixed intervals for transfer of the pixels corresponding to the respective locations.

8. The image digitizer of claim 5, wherein the means for transferring causes a plurality of pixels to be transferred in response to a single address and wherein the means for transferring transfers pixels while allowing the processor to address other memory locations.

9. The image digitizer of claim 5, wherein the pixel engine transfers a plurality of pixels in response to a single memory address from the processor in a single memory cycle.

10. An image digitizer comprising:

a video memory for storing digital pixel data at memory locations;

an interface;

a processor including

means for processing pixel data, and

means for addressing memory locations to identify selected pixel data;

a pixel engine connected between the video memory and the processor, and between the video memory and the interface, the pixel engine including

means for transfering pixel data representing a plurality of pixels between the video memory and the interface independent of the processor in response to a single first type of address to a particular location from the processor,

means for coupling the processor to the video memory to allow the means for processing to process the pixel data at a particular location in video memory in response to a second type of address from the processor,

means for determining whether the processor is addressing the particular memory location for processing or for transferring based on whether the address is of a first type or a second type.