Non-volatile semiconductor memory device

• US 5,453,955 A
• Filed: 06/07/1994
• Issued: 09/26/1995
• Est. Priority Date: 03/04/1991
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Masuoka, Fujio, Nakamura, Hiroshi, Shirota, Riichiro, Momodomi, Masaki, Sakui, Koji
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US08/255,904
• Time in Patent Office: 476 Days
• Field of Search: 365/203, 365/233, 365/233.5, 365/190, 365/204
• US Class Current: 365/203
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A non-volatile semiconductor memory device includes read charging transistors for setting bit lines at a predetermined read potential to perform a data read operation, and read discharging transistors for setting non-selected bit lines at the ground potential during the read operation. These transistors are controlled by different control signals, obtained by detecting an address change, for every other bit line in accordance with an input address so that the read discharging transistors are kept ON to set the non-selected bit lines at the ground potential before and during the data read operation.

Claims

1. A non-volatile semiconductor memory device comprising:

a plurality of bit lines which are selected in accordance with an input address;

a plurality of word lines arranged to intersect said bit lines;

a plurality of erasable programmable non-volatile semiconductor memory cells respectively arranged at each intersecting position between said bit lines and said word lines and driven by said word lines to transfer data to said bit lines;

a plurality of sense amplifiers, respectively connected to said bit lines, for detecting data of the memory cells selected by said word lines; and

precharge means, connected to said bit lines and controlled by a control signal obtained by detecting an input address, for fixing non-selected bit lines at a predetermined potential,

wherein said precharge means comprises a plurality of read charging transistors for setting the selected bit lines at a predetermined read potential to perform a data read operation, and a plurality of read discharging transistors for setting the non-selected bit lines at a ground potential during a read operation, said read charging transistors and said read discharging transistors being controlled by different control signals, obtained by detecting change of the address, for every other bit line in accordance with the input address, and said read discharging transistors being kept ON to maintain said non-selected bit lines at the ground potential before and during a data read operation.

2. The device according to claim 1, wherein said non-volatile semiconductor memory cells are electrically erasable programmable non-volatile semiconductor memory cells which are connected in series so as to constitute units of a plurality of cells.

3. A non-volatile semiconductor memory device comprising:

a plurality of bit lines which are selected in accordance with an input address;

a plurality of word lines arranged to intersect said bit lines;

a plurality of erasable programmable non-volatile semiconductor memory cells respectively arranged at each intersecting position between said bit lines and said word lines and driven by said word lines to transfer data to said bit lines;

a plurality of sense amplifiers, respectively connected to said bit lines, for detecting data of the memory cells selected by said word lines; and

precharge means, connected to said bit lines and controlled by a control signal obtained by detecting an input address, for fixing non-selected bit lines at a predetermined potential,

wherein said precharge means comprises a plurality of write charging transistors for setting the selected bit lines at an intermediate potential to perform a data write operation, said write charging transistors being controlled by different control signals, obtained by detecting an address change, for every other bit line in accordance with the input address, said write charging transistors connected to the selected bit lines being turned off for a data write operation, and said write charging transistors connected to the non-selected bit lines being kept ON during the data write operation.

4. The device according to claim 3, wherein said non-volatile semiconductor memory cells are electrically erasable programmable non-volatile semiconductor memory cells which are connected in series so as to constitute units of a plurality of cells.

5. A non-volatile semiconductor memory device comprising:

a plurality of bit lines which are selected in accordance with an input address;

a plurality of word lines arranged to intersect with said bit lines;

a plurality of erasable programmable non-volatile semiconductor memory cells respectively arranged at each intersecting position between said bit lines and said word lines and driven by said word lines to exchange data with said bit lines;

a plurality of sense amplifiers, respectively connected to said bit lines, for detecting data of the memory cells selected by said word lines; and

precharge means connected to said bit lines, for fixing the bit lines at least every other bit line at a predetermined potential in accordance with the input address,

wherein said precharge means includes;

at least first and second pairs of control lines arranged to intersect said bit lines;

a plurality of first switching transistors arranged at a plurality of intersecting positions between said bit lines and said first pair of control lines at least every other bit line and connected to said bit lines and said control lines, for selectively connecting the bit lines connected to one of said first pair of control lines and those of the other to a data reading potential to perform a data read operation; and

a plurality of second switching transistors arranged at a plurality of intersecting positions between said bit lines and said second pair of control lines at least every other bit line and connected to said bit lines and said control lines, for selectively connecting the bit lines connected to one of said second pair of control lines and those of the other to a shield potential lower than the data reading potential.

6. The device according to claim 5, wherein said non-volatile semiconductor memory cells are electrically erasable and programmable non-volatile semiconductor memory cells which are connected in series so as to constitute units of a plurality of cells.

7. The memory device according to claim 5, wherein said precharge means includes:

a pair of write control lines arranged to intersect said bit lines; and

a plurality of write charging transistors arranged at a plurality of intersecting positions between said bit lines and said pair of write control lines at least every two bit lines and connected to said bit lines and said write control lines, for setting the selected bit lines at an intermediate potential to perform a data write operation, said write charging transistors being controlled by different control signals, obtained by detecting an address change, for every other bit line in accordance with the input address, said write charging transistors connected to the selected bit lines being turned off before a data write operation, and said write charging transistors connected to the non-selected bit lines being kept ON during the data write operation.

8. A non-volatile semiconductor memory device comprising:

a plurality of bit lines which are selected in accordance with an input address;

a plurality of word lines arranged to intersect said bit lines;

a plurality of erasable programmable non-volatile semiconductor memory cells respectively arranged at each intersecting position between said bit lines and said word lines and driven by said word lines to exchange data with said bit lines;

a plurality of sense amplifiers, respectively connected to said bit lines, for detecting data of the memory cells selected by said word lines; and

precharge means connected to said bit lines, for fixing the bit lines at least every other bit line at a predetermined potential in accordance with the input address,

wherein said precharge means includes;

a pair of write control lines arranged to intersect said bit lines; and

a plurality of write charging transistors arranged at a plurality of intersecting positions between said bit lines and said pair of write control lines at least every two bit lines and connected to said bit lines and said write control lines, for setting the selected bit lines at an intermediate potential to perform a data write operation, said write charging transistors being controlled by different control signals, obtained by detecting an address change, for every other bit line in accordance with the input address, said write charging transistors connected to the selected bit lines being turned off before a data write operation, and said write charging transistors connected to the non-selected bit lines being kept ON during the data write operation.

9. The device according to claim 8, wherein said non-volatile semiconductor memory cells are electrically erasable programmable non-volatile semiconductor memory cells which are connected in series so as to constitute units of a plurality of cells.

10. A non-volatile semiconductor memory device comprising:

a plurality of bit lines which are selected in accordance with an input address;

a plurality of word lines arranged to intersect said bit lines;

a plurality of erasable programmable non-volatile semiconductor memory cells respectively arranged at each intersecting position between said bit lines and said word lines and driven by said word lines to transfer data to said bit lines;

a plurality of sense amplifiers, respectively connected to said bit lines, for detecting data of the memory cells selected by said word lines; and

bit line shielding means, connected to said bit lines and controlled by a control signal obtained by detecting an input address, for fixing non-selected bit lines at a predetermined potential with respect to selected bit lines to electrically shield the selected bit lines;

wherein said non-volatile semiconductor memory cells are electrically erasable programmable non-volatile semiconductor memory cells which are connected in series so as to constitute units of a plurality of cells.

11. An erasable programmable non-volatile semiconductor memory device comprising:

a plurality of bit lines divided into at least first and second bit line groups, the bit lines of said first bit line group being alternately arranged;

a plurality of word lines arranged to intersect said bit lines;

a plurality of erasable non-volatile semiconductor memory cells respectively arranged at each intersecting position between said bit lines and said word lines, and driven by said word lines to transfer data to said bit lines;

a plurality of sense amplifiers connected to said bit lines, for detecting data from the memory cells selected by said word lines;

selection means for selecting one of said first and second bit line groups in accordance with an address input to said memory device;

precharge means for fixing the bit lines of the bit line group not selected by said selection means at a ground potential in at least a data reading mode;

a plurality of switching transistors connected between said bit lines and said sense amplifiers; and

means for driving said switching transistors in pairs, wherein two adjacent switching transistors are connected to one or more of said sense amplifiers.