Method of shaping inter-substrate plug and receptacles interconnects

• US 5,457,879 A
• Filed: 01/04/1994
• Issued: 10/17/1995
• Est. Priority Date: 01/04/1994
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hughes, Henry G., Gurtler, Richard W.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US08/177,024
• Time in Patent Office: 651 Days
• Field of Search: 156/630, 156/633, 156/635, 156/901, 29/825, 29/830, 29/845, 437/192
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13019 at the bonding interface of the bump connector, i.e. on the surface of the bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81899 using resilient parts in the bump connector or in the bonding area
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/32 Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49153 : with shaping or forcing terminal into base aperture

Abstract

A method electrically and mechanically interconnects two surfaces of high density first and second semiconductor devices. The first semiconductor device (10) is formed with plug members (22) connected to nodes (18) of its circuit elements (14) and protruding from the first semiconductor device. The second semiconductor device (24) is formed having receptacle members (36) connected to nodes (32) of its circuit elements (28) and protruding from the second semiconductor device. The plug members are inserted into the receptacle member to interconnect the first and second semiconductor devices. The plug members may be removed from the receptacle member to disconnect the first and second semiconductor devices.

Claims

1. A method of connecting first and second semiconductor substrates, comprising the steps of:

forming a plug member on the first semiconductor substrate coupled to a node of the first semiconductor substrate; and

forming a receptacle member on the second semiconductor substrate coupled to a node of the second semiconductor substrate, said plug member being adapted for insertion into said receptacle member to interconnect the first and second semiconductor substrates.

2. The method of claim 1 wherein said step of forming a receptacle member includes the steps of:

providing the second substrate with an isolation layer disposed on said node of the second substrate; and

disposing a dielectric layer having a predetermined variation in composition on said isolation layer to achieve an etch rate varying with height above said isolation layer.

3. The method of claim 2 wherein said step of forming a receptacle member includes the step of depositing a masking layer on said dielectric layer.

4. The method of claim 3 wherein said step of forming a receptacle member further includes the steps of:

etching said dielectric to form a shaped region dependent on said varying etch rate; and

etching said isolation layer to expose a portion of said nodes below said shaped region.

5. The method of claim 4 wherein said step of forming a receptacle member includes the steps of:

stripping said masking layer;

depositing a conformal conducting layer in said shaped region to form a receptacle wall; and

removing said dielectric layer by etching process to leave said receptacle member protruding from the second substrate.

6. A method of connecting first and second substrates, comprising the steps of:

forming a plug member on the first substrate coupled to a node of the first substrate, said step of forming said plug member further including the steps of,

(a) providing the first substrate with an isolation layer disposed on said node of the first substrate, and

(b) disposing a dielectric layer having a predetermined variation in composition on said isolation layer to achieve an etch rate varying with height above said isolation layer; and

forming a receptacle member on the second substrate coupled to a node of the second substrate, said plug member being adapted for insertion into said receptacle member to interconnect the first and second substrates.

7. The method of claim 6 wherein said step of forming a plug member includes the step of depositing a masking layer on said dielectric layer.

8. The method of claim 7 wherein said step of forming a plug member further includes the step of etching said dielectric to form a shaped region dependent on said varying etch rate.

9. The method of claim 8 wherein said step of forming a plug member includes the steps of:

stripping said masking layer;

filling said shaped region with a conductive material; and

removing said dielectric layer by etching process to leave said plug member protruding from the first substrate.

10. A method of connecting first and second semiconductor substrates, comprising the steps of:

forming a plug member on the first semiconductor substrate coupled to a node of the first semiconductor substrate;

forming a receptacle member on the second semiconductor substrate coupled to a node of the second semiconductor substrate;

inserting said plug member into said receptacle member to interconnect the first and second semiconductor substrates; and

removing said plug member from said receptacle member to disconnect the first and second semiconductor substrates.

11. The method of claim 10 wherein said step of forming a plug member includes the steps of:

providing the first substrate with an isolation layer disposed on said node of the first substrate; and

disposing a dielectric layer having a predetermined variation in composition on said isolation layer to achieve an etch rate varying with height above said isolation layer.

12. The method of claim 11 wherein said step of forming a plug member includes the step of depositing a masking layer on said dielectric layer.

13. The method of claim 12 wherein said step of forming a plug member further includes the steps of:

etching said dielectric to form a shaped region dependent on said varying etch rate;

stripping said masking layer;

filling said shaped region with a conductive material; and

removing said dielectric layer by etching process to leave said plug member protruding from the first substrate.

14. The method of claim 10 wherein said step of forming a receptacle member includes the steps of:

providing the second substrate with an isolation layer disposed on said node of the second substrate; and

disposing a dielectric layer having a predetermined variation in composition on said isolation layer to achieve an etch rate varying with height above said isolation layer.

15. The method of claim 14 wherein said step of forming a receptacle member includes the step of depositing a masking layer on said dielectric layer.

16. The method of claim 15 wherein said step of forming a receptacle member further includes the steps of:

etching said dielectric to form shaped regions dependent on said varying etch rate; and

etching said isolation layer to expose a portion of said node below said shaped region.

17. The method of claim 16 wherein said step of forming a receptacle member includes the steps of:

stripping said masking layer;

depositing a conformal layer in said shaped region to form a receptacle wall; and

removing said dielectric layer by etching process to leave said receptacle member protruding from the second substrate.