CMOS image sensor with pixel level A/D conversion

• US 5,461,425 A
• Filed: 02/15/1994
• Issued: 10/24/1995
• Est. Priority Date: 02/15/1994
• Status: Expired due to Term

• Current Assignee: Stanford University
• Original Assignee: Stanford University
• Inventors: Fowler, Boyd, El Gamal, Abbas
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Burgess, Glenton B.
• Application Number:
  US08/196,686
• Time in Patent Office: 616 Days
• Field of Search: 348/222, 348/227, 348/230, 348/236, 348/294, 348/304, 348/311, 348/312, 348/297, 348/298, 257/291, 257/292, 250/208.1, 250/200.1
• US Class Current: 348/294
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/456 the modulator having a first order loop filter in the feedforward path
• CPC Class Codes: H03M 3/466 Multiplexed conversion systems
• CPC Class Codes: H04N 25/51 Control of the gain
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An image sensor formed using a CMOS process is described herein which includes a pixel array core of phototransistors whose conductivities are related to the magnitude of light impinging upon the phototransistors. The analog signals generated by the phototransistors are converted to a serial bit stream by an A/D converter connected at the output of each phototransistor and formed in the immediate area of each phototransistor within the array core. Thus, a separate digital stream for each pixel element is output from the array core, and parasitic effects and distortion are minimized. In one embodiment, a filter circuit is connected to an output of the array core for converting the individual digital streams from each pixel element to multi-bit values corresponding to the intensity of light impinging on the phototransistor.

Claims

1. An image sensor circuit comprising:

a two dimensional array of photodetectors located within an image sensor core on an integrated circuit chip, each of said photodetectors having electrical characteristics which vary in response to light impinging upon said photodetectors; and

a plurality of analog-to-digital (A/D) converters located within said two dimensional array of photodetectors within said image sensor core, each of said A/D converters being located in a separate pixel area containing one or more of said photodetectors, each of said converters being connected to said one or more of said photodetectors in said pixel area for converting an analog output of said one or more photodetectors to binary signals, an output of each pixel area in said image sensor core comprising said binary signals.

2. The circuit of claim 1 wherein each of said A/D converters comprises an A/D converter for converting said analog output of said one or more photodetectors to a string of binary bits to be output from said image sensor core.

3. The circuit of claim 2 further comprising a plurality of filters which receive strings of said binary bits output from said image sensor core and convert said strings of binary bits to digital values representative of a light intensity impinging upon respective photodetectors over a period of time.

4. The circuit of claim 1 wherein said A/D converters comprise Sigma-Delta modulators.

5. The circuit of claim 1 wherein all of said A/D converters are clocked simultaneously to simultaneously output binary signals from said image sensor core.

6. The circuit of claim 1 further comprising a row decoder, wherein said binary signals are output from said image sensor core by addressing rows of said A/D converters and causing an output of each A/D converter in an addressed row to be provided on a respective bit line in said image sensor core.

7. The circuit of claim 1 wherein each of said photodetectors is connected to a dedicated one of said A/D converters within said image sensor core.

8. The circuit of claim 1 wherein said array of photodetectors comprises an array greater than or equal to a 16×

16 array.

9. The circuit of claim 1 wherein said array of photodetectors comprises an array greater than or equal to a 64×

64 array.

10. The circuit of claim 1 further comprising:

a plurality of filters which receive strings of binary bits output from said A/D converters and convert said strings of binary bits to digital values representative of a light intensity impinging upon respective photodetectors over a period of time;

a memory for storing said digital values generated by said filters; and

a control circuit for transferring said digital values from said filters to storage locations within said memory and for transferring said digital values from said memory to said filters for further processing by said filters as new data is being output from said image sensor core, said new data being processed by said filters to update said digital values which have been transferred from said memory to said filters, said control circuit then transferring updated digital values back to said memory.

11. The circuit of claim 1 further comprising data compression circuitry contained within said core for reducing a bandwidth of data output by each pixel area for detection outside of said core.

12. The circuit of claim 1 further comprising data compression circuitry contained outside of said core for reducing a bandwidth of data output from said integrated circuit chip.

13. A method for generating electrical signals representing an optical image, said method comprising the steps of:

generating an analog signal at each pixel location in a two dimensional array of photodetectors within an image sensor core, said analog signal corresponding to a light intensity impinging on said each pixel location;

converting said analog signal to digital signals at said each pixel location within said two dimensional array of photodetectors such that said each pixel location within said two dimensional array of photodetectors provides digital output signals representing a level of said analog signal; and

processing said digital signals generated within said each pixel location to derive a single digital value associated with said each pixel location corresponding to said analog signal at said each pixel location over a period of time.

14. The method of claim 13 wherein said step of converting said analog signal to digital signals comprises converting said analog signal to a string of binary bits.

15. The method of claim 14 wherein said step of converting said analog signal comprises performing multiple one-bit analog-to-digital (A/D) conversions of said analog signal over a period of time.

16. The method of claim 15 wherein an A/D converter is located within said each pixel location, and wherein all A/D converters within said image sensor core are clocked using a single clock source.

17. The method of claim 16 wherein said each pixel location includes one or more photodetectors.

18. The method of claim 16 wherein said each pixel location includes one photodetector and one A/D converter.