Method and apparatus for encoding/decoding image data

• US 5,461,679 A
• Filed: 05/14/1993
• Issued: 10/24/1995
• Est. Priority Date: 05/24/1991
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Wright, Daniel W., Yeh, Chia L., Chu, Ke-Chiang, Normile, James O.
• Primary Examiner(s): COUSO, YON JUNG
• Application Number:
  US08/062,067
• Time in Patent Office: 893 Days
• Field of Search: 382/56, 382/27, 382/41, 382/49, 340/752, 364/133, 395/114, 395/115, 395/425
• US Class Current: 382/304
• CPC Class Codes: H04N 19/107 between spatial and temporal predictive coding, e.g. picture refresh
• CPC Class Codes: H04N 19/30 using hierarchical techniques, e.g. scalability H04N19/63 takes precedence
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/503 involving temporal prediction adaptive coding with adaptive selection between spatial and temporal predictive coding H04N19/107; adaptive coding with adaptive selection among a plurality of temporal predictive coding modes H04N19/109
• CPC Class Codes: H04N 19/51 Motion estimation or motion compensation
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/236 Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream multiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 5/783 Adaptations for reproducing at a rate different from the recording rate
• CPC Class Codes: H04N 5/85 on discs or drums
• CPC Class Codes: H04N 7/54 the signals being synchronous H04N21/23602, H04N21/23614, H04N21/2365, H04N21/2368, H04N21/4341, H04N21/4342, H04N21/4347, H04N21/4348 take precedence
• CPC Class Codes: H04N 9/8047 using transform coding

Abstract

An apparatus and method for processing video data for compression/decompression in real-time. The apparatus comprises a plurality of compute modules, in a preferred embodiment, for a total of four compute modules coupled in parallel. Each of the compute modules has a processor, dual port memory, scratch-pad memory, and an arbitration mechanism. A first bus couples the compute modules and a host processor. Lastly, the device comprises a shared memory which is coupled to the host processor and to the compute modules with a second bus. The method handles assigning portions of the image for each of the processors to operate upon.

Claims

1. A processing apparatus for processing variable length input data to generate variable length output data comprising:

a. an input circuit for providing said input data;

b. a plurality of processing modules coupled to said input circuit for processing said input data;

c. a shared memory coupled to said input circuit and said plurality of processing modules, said shared memory for receiving said input data from said input circuit, providing said input data to said plurality of processing modules, for posting jobs to be processed by said plurality of processing modules, and for providing communication between said plurality of processing modules and said input circuit;

d. a first bus coupled to said plurality of processing modules and said shared memory, said first bus for transmitting said input data from said shared memory to said plurality of processing modules, said first bus including variable precision communication means allowing said input data to be of variable length and/or variable precision;

e. an output circuit coupled to said plurality of processing modules for receiving said output data; and

f. a second bus coupled to said input circuit and said plurality of processing modules, each of said plurality of processing modules including;

i. a processor for processing said jobs posted in said shared memory, certain of said jobs allocated to said processing module for processing a portion of said input data to create a portion of said output data, wherein said portion of said input or said output data may be variable in length or precision according to operating circumstances;

ii. a dual-port memory coupled to said processor and said second bus for providing communication between said processing module and said input circuit;

iii. a processor memory coupled to said processor for processing said portion of said input data; and

iv. an arbitration mechanism coupled to said processor for allowing said processing module to request and obtain access to said shared memory for receiving said certain jobs allocated to said processing module to receive said portion of said input data.

2. The apparatus of claim 1 wherein said input circuit includes a host processor.

3. The apparatus of claim 1 wherein said output circuit includes a display circuit.

4. The apparatus of claim 3 wherein said display circuit includes a display controller, frame buffer and display.

5. The apparatus of claim 1 further comprising a frame buffer and display coupled to said first bus.

6. The apparatus of claim 1 wherein said input data includes compressed video data and said output data includes uncompressed video data.

7. The apparatus of claim 1 wherein said input data includes uncompressed video data and said output data includes compressed video data.

8. The apparatus of claim 1 wherein one of said plurality of processing modules is a master processing module and said master processing module further comprises:

a. input data request circuitry for requesting that said input circuit place said input data into said shared memory;

b. job creation circuitry for creating said jobs for processing by each of said plurality of processing modules and placing said jobs into said shared memory, said job creation circuitry including apportioning circuitry for apportioning said input data into portions for each of said jobs; and

c. processing circuitry for processing said jobs upon completion of creating said jobs.

9. The apparatus of claim 8 wherein a remainder of said plurality of processing modules are slave processing modules, each of said slave modules comprising said processing circuitry for processing said jobs.

10. The apparatus of claim 8 wherein said job creation circuitry includes a stack creation circuit for organizing said jobs into a job stack in said shared memory for accessing by each of said plurality of processing modules.

11. The apparatus of claim 10 wherein each of said plurality of processing modules includes a stack accessing circuit for accessing said stack to receive jobs for processing by each of said plurality of processing modules, said stack accessing circuit in said each of said plurality of processing modules operative upon completion of a previous job by said each of said plurality of processing modules.

12. The apparatus of claim 1 wherein said output circuit is coupled to said second bus and each of said plurality of processing modules includes a buffer circuit for placing said portion of said output data in said dual-port memory and said output circuit includes a request circuit for requesting each said portion of said output data from each said dual-port memory of each of said plurality of processing modules.

13. The apparatus of claim 1 wherein said output circuit is coupled to said first bus and each of said plurality of processing modules includes a buffer circuit for placing said output data in said shared memory and said output circuit includes a request circuit for requesting said output data from said shared memory.

14. A processing apparatus for processing variable length input data to generate variable length output data comprising:

a. an input circuit for providing said input data;

b. a plurality of processing modules coupled to said input circuit for processing said input data;

c. a shared memory coupled to said input circuit and said plurality of processing modules, said shared memory for receiving said input data from said input circuit, providing said input data to said plurality of processing modules, for posting jobs to be processed by said plurality of processing modules, for receiving said output data from said plurality of processing modules and for providing communication between said plurality of processing modules and said input circuit;

d. a processing bus coupled to said plurality of processing modules and said shared memory, said processing bus for transmitting said input data from said shared memory to said plurality of processing modules and for transmitting said output data from said plurality of processing modules to said shared memory, said processing bus including variable precision communication means allowing said input and said output data to be of variable precision; and

e. an output circuit coupled to said plurality of processing modules for receiving said output data.

15. The apparatus of claim 14 wherein each of said plurality of processing modules includes:

a. a processor for processing said jobs posted in said shared memory, certain of said jobs allocated to said processing module for processing a portion of said input data to create a portion of said output data, wherein said portion of said input or said output data may be variable in length or precision according to operating circumstances;

b. a processor memory coupled to said processor for processing said portion of said input data; and

c. an arbitration mechanism coupled to said processor for allowing said processing module to request and obtain access to said shared memory for receiving said certain jobs allocated to said processing module, to receive said portion of said input data, and to provide said portion of said output data to said shared memory.