Method and apparatus for entering a low-power mode and controlling an external bus of a data processing system during low-power mode

• US 5,471,625 A
• Filed: 09/27/1993
• Issued: 11/28/1995
• Est. Priority Date: 09/27/1993
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Mussemann, Gary A., Gay, James G., Circello, Joseph C.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US08/125,851
• Time in Patent Office: 792 Days
• Field of Search: 364/492, 364/200, 295/750, 295/425, 295/200, 295/800, 295/325
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

A method and apparatus for placing a data processor (12) into a low-power mode of operation using a system (10). The system (10) has a processor (12). The processor (12) has access to a bus (18). The bus (18) is coupled to a bus controller (14). The processor (12) sends a broadcast cycle out through the bus (18) when the processor (12) desires to enter a low-power mode of operation. The bus controller (14) determines that the broadcast cycle has been sent on the bus (18). The bus controller (14) waits a predetermined amount of time to process the low-power request and grants permission to the processor (12) to enter the low-power mode via the communication of a transmission termination signal. The processor (12) conditionally drives either logic ones or a tri-state value onto the bus (18) depending upon whether or not the processor (12) has been granted ownership of the bus (18).

Claims

1. A method for controlling a bus within a data processing system, the data processing system having a data processor coupled by at least one control bit line to circuitry for providing bus management, the method comprising:

determining that the data processor is to be placed into a low-power mode;

performing a low-power mode broadcast through the bus wherein the data processor communicates to the circuitry for providing bus management that the data processor is to be placed into a low-power mode of operation;

placing the data processor into a state wherein the data processor waits for the circuitry for providing bus management to communicate permission to the data processor to enter low-power mode, the permission being sent within an amount of time determined by the circuitry for providing bus management; and

determining via the circuitry for providing bus management whether the data processor is to drive the bus to a predetermined plurality of voltage values or electrically tri-state the bus when in the low-power mode of operation.

2. The method of claim 1 wherein the step of determining via the circuitry for providing bus management comprises the step of:

driving the predetermined plurality of voltage values as voltage values selected from a group consisting of;

all binary one values and all binary zero values.

3. The method of claim 1 wherein the step of placing the data processor into a state wherein the data processor waits for the circuitry for providing bus management to communicate permission comprises the step of:

sending either a transfer acknowledge (TA) signal or a transfer error acknowledge (TEA) signal from the circuitry for providing bus management to the data processor to give the data processor permission to enter the low-power mode of operation.

4. The method of claim 1 wherein the step of placing the data processor into a state wherein the data processor waits for the circuitry for providing bus management to communicate permission comprises the step of:

placing the data processor into the low-power mode of operation after a predetermined watchdog time period if no response to the broadcast is received from the circuitry for providing bus management within the predetermined watchdog time period.

5. The method of claim 1 wherein the step of placing the data processor into a state wherein the data processor waits for the circuitry for providing bus management to communicate permission comprises the step of:

preempting the data processor from entering the low-power mode of operation if the circuitry for providing bus management determines that the data processor should not be placed into a low-power mode of operation.

6. The method of claim 1 wherein the step of placing the data processor into a state wherein the data processor waits for the circuitry for providing bus management to communicate permission comprises the step of:

changing access to the bus in response to the low-power mode of operation being requested by the data processor.

7. The method of claim 6 wherein the step of changing access to the bus comprises the step of:

changing access to the bus before the data processor is given permission to enter the low-power mode of operation.

8. The method of claim 1 wherein the circuitry for providing bus management communicates to the data processor a binary bus grant signal wherein the binary bus grant signal informs the data processor whether the bus is accessible to the data processor.

9. The method of claim 1 wherein the step of determining via the circuitry for providing bus management comprises the step of:

driving the bus to a tri-state condition if the data processor does not currently have ownership of the bus.

10. The method of claim 1 wherein the step of determining via the circuitry for providing bus management comprises the step of:

driving the bus to logic one values if the data processor currently has ownership of the bus.

11. A bus protocol for controlling a bus having at least one bit, the bus protocol controlling the bus in a manner which allows a data processor, which is coupled to the bus, to selectively enter a low-power mode of operation, the data processor having a bus grant status which determines the data processor ability to communicate with the bus, the method comprising:

broadcasting a request on the bus, the request being broadcast by the data processor to indicate external to the data processor that the data processor intends to enter into a low-power mode of operation;

placing the data processor into a mode wherein the data processor waits for a permission signal from the bus which allows the data processor to enter the low-power mode of operation;

allowing the data processor to enter the low-power mode of operation if either the permission signal is received from the bus or a predetermined amount of time passes and a watchdog permission signal is received from external to the data processor;

placing the data processor into a state wherein the at least one bit of the bus is driven to an electrical value, the electrical value being determined by the bus grant state of the data processor.

12. The method of claim 11 wherein the step of placing the data processor into a state comprises the step of:

driving the at least one bit of the bus to a value selected from a group consisting of;

a binary one value, a binary zero value, a tri-state value.

13. The method of claim 11 wherein circuitry for controlling ownership to the bus is coupled to the data processor, the circuitry for controlling the bus communicating the permission signal to the data processor.

14. A system comprising:

an execution unit for executing computer instructions, the execution unit having a normal mode of operation and a low-power mode of operation, the low-power mode of operation is entered by broadcasting a low-power request external to the execution unit and waiting for the execution unit to receive permission to enter the low-power mode of operation from external to the execution unit;

a bus coupled to the means for executing computer instructions, the bus having at least one conductor for communicating information within the system, the at least one conductor being used to transmit the low-power request; and

a bus controller coupled to the means for executing computer instructions through the bus, the bus controller granting the means for executing computer instructions selective access to the bus, the bus controller receiving the low-power request from the bus and sending the permission to enter the low-power mode of operation to the means for executing computer instructions, a time between the receipt of the low-power request and the sending of the permission being variable depending upon an amount of low-power mode preparation that is performed by the bus controller in order to prepare the system for the means for executing entering the low-power mode of operation.

15. The system of claim 14 wherein the means for executing computer instructions drives a set of values onto the bus when in the low-power mode of operation, the set of values being selected from a group consisting of:

binary zeros, binary ones, and tri-state signals.

16. The system of claim 14 further comprising:

an alternate means for executing computer instructions coupled to the bus controller and the bus, the alternate means for executing computer instructions having access to the bus during times when the means for executing computer instructions does not have bus access.

17. The system of claim 14 further comprising:

one or more peripheral devices coupled to the bus, the peripheral devices being selectively accessed by the means for executing computer instructions through the bus.

18. The system of claim 14 wherein the access to the bus is changed by the bus controller after the means for executing computer instructions sends the low-power request and before the permission is transmitted.

19. The system of claim 14 wherein the means for executing computer instructions enters the low-power mode of operation after waiting a predetermined amount of time wherein at the end of the predetermined amount of time a transfer termination signal generated in response to a watchdog circuit is received.

20. The system of claim 14 further comprising:

a bus grant conductor coupling the means for executing and the bus controller, the bus grant conductor allowing the bus controller to signal the means for executing whether the means for execution has exclusive access to the bus; and

a bus request conductor coupling the means for executing and the bus controller, the bus request conductor allowing the means for executing to request exclusive access of the bus from the bus controller.

21. A method for allowing a processor to enter a low-power mode of operation comprising:

sending data external to the processor using a bus coupled to the processor, the data being used to indicate that the low-power mode of operation is requested;

placing the processor into a mode wherein the processor waits for receipt of an externally-generated bus cycle termination control signal which signifies that the data has been processed, the time between the sending of the data and the receipt of the externally-generated bus cycle termination control signal being variable; and

entering the low-power mode of operation in response to the externally-generated bus cycle termination control signal.

22. The method of claim 21 wherein the step of entering comprises:

shutting down a clock signal which is coupled as an input to the processor.

23. A method for placing a system into a low-power mode of operation, the system having a processor and a bus controller, the method comprising:

informing the bus controller that the processor desires to enter a low-power mode of operation;

generating a permission control signal in the bus controller and transmitting the permission control signal to the processor, the permission control signal indicating that the processor may enter the low-power mode of operation;

placing the processor into a low power mode of operation;

informing the bus controller that the processor has entered the low power mode of operation; and

placing at least one peripheral into a low-power mode of operation in response to the processor being placed into the low-power mode of operation.

24. The method of claim 23 wherein the step of placing at least one peripheral into a low-power mode of operation comprises:

turning off at least one clock signal which is input into the processor.