Switched capacitance voltage multiplier with commutation
First Claim
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1. A d.c. to a.c. voltage multiplier circuit comprising:
- (a) a series network comprising a plurality of capacitors, each of said capacitors having a sufficient mount of capacitance to substantially maintain a charge voltage over a period of an a.c. output waveform;
(b) a plurality of switches for selectably coupling said each of said capacitors to a d.c. input voltage for a selected charging time at least once during said period wherein said series network produces a sequentially increasing voltage followed by a sequentially decreasing voltage during one half of said period to form a waveform half;
(c) a pair of output terminals; and
(d) a commutator circuit interposed between said pair of output terminals and said series network, said commutator circuit selectively coupling said output terminals to receive said waveform half in a positive polarity followed by a negative polarity to form said a.c. output waveform at said pair of output terminals.
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Abstract
A voltage multiplier is constructed using a series combination of capacitors and an associated switching circuit which provides for charging each capacitor in the series by sequentially connecting each capacitor to a d.c. input voltage. The d.c. input voltage of N volts is converted to an a.c. output voltage of peak-to-peak 2*(N+1) times the input voltage where N is the number of capacitors in the series. A pattern of sequential switching is chosen to generate a sequentially rising and falling voltage to form a half waveform. A commutator couples the half waveform to a pair of output terminals in an alternating polarity to form the completed a.c. output voltage.
36 Citations
5 Claims
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1. A d.c. to a.c. voltage multiplier circuit comprising:
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(a) a series network comprising a plurality of capacitors, each of said capacitors having a sufficient mount of capacitance to substantially maintain a charge voltage over a period of an a.c. output waveform; (b) a plurality of switches for selectably coupling said each of said capacitors to a d.c. input voltage for a selected charging time at least once during said period wherein said series network produces a sequentially increasing voltage followed by a sequentially decreasing voltage during one half of said period to form a waveform half; (c) a pair of output terminals; and (d) a commutator circuit interposed between said pair of output terminals and said series network, said commutator circuit selectively coupling said output terminals to receive said waveform half in a positive polarity followed by a negative polarity to form said a.c. output waveform at said pair of output terminals. - View Dependent Claims (2, 3, 4, 5)
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Specification