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Switched capacitance voltage multiplier with commutation

  • US 5,481,447 A
  • Filed: 04/27/1995
  • Issued: 01/02/1996
  • Est. Priority Date: 04/27/1995
  • Status: Expired due to Term
First Claim
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1. A d.c. to a.c. voltage multiplier circuit comprising:

  • (a) a series network comprising a plurality of capacitors, each of said capacitors having a sufficient mount of capacitance to substantially maintain a charge voltage over a period of an a.c. output waveform;

    (b) a plurality of switches for selectably coupling said each of said capacitors to a d.c. input voltage for a selected charging time at least once during said period wherein said series network produces a sequentially increasing voltage followed by a sequentially decreasing voltage during one half of said period to form a waveform half;

    (c) a pair of output terminals; and

    (d) a commutator circuit interposed between said pair of output terminals and said series network, said commutator circuit selectively coupling said output terminals to receive said waveform half in a positive polarity followed by a negative polarity to form said a.c. output waveform at said pair of output terminals.

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