Static-random-access memory cell and an integrated circuit having a static-random-access memory cell

• US 5,485,420 A
• Filed: 07/21/1994
• Issued: 01/16/1996
• Est. Priority Date: 12/11/1992
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lage, Craig S., Cooper, Kent J., Hayden, James D., Baker, Frank K.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US08/278,465
• Time in Patent Office: 544 Days
• Field of Search: 365/154, 365/149, 365/182, 257/277, 257/303, 257/903
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

Claims

1. A static-random-access memory cell comprising:

a first capacitor having a first plate and a second plate, wherein;

the first plate of the first capacitor includes a first plate section of a gate electrode of a first transistor;

the second plate of the first capacitor overlies the first plate of the first capacitor;

the first and second plates of the first capacitor are substantially coincident with each other; and

the first capacitor is located within the memory cell; and

a first conductive member that is electrically connected to;

the second plate of the first capacitor; and

a first region of the memory cell, wherein the first region;

lies within a substrate; and

is selected from a group consisting of a source/drain region, a source region, and a drain region.

2. The memory cell of claim 1, wherein:

the first transistor is a first latch transistor further including a source region and a drain region;

the memory cell further includes;

a second latch transistor including a source region, a drain region, and a gate electrode having a first plate section;

a second capacitor having a first plate and a second plate, wherein;

the first plate includes the first plate section of the gate electrode of the second latch transistor;

the second plate includes a second conductive member; and

both plates of the second capacitor are substantially coincident with each other;

a first pass transistor having a first source/drain region, a second source/drain region, and a gate electrode;

a second pass transistor having a first source/drain region, a second source/drain region, and a gate electrode;

a first component having a storage node section and an electrode section, wherein the first component is selected from a group consisting of a resistor and a transistor; and

a second component having a storage node section and an electrode section, wherein the first component is selected from a group consisting of a resistor and a transistor; and

the memory cell is configured such that;

the first pass transistor, the first latch transistor, and the first component are associated with a first storage node;

the second pass transistor, the second latch transistor, and the second component are associated with a second storage node;

the drain region of the first latch transistor, the storage node section of the first component, the second source/drain region of the first pass transistor, and the gate electrode of the second latch transistor are electrically connected to one another;

the drain region of the second latch transistor, the storage node section of the second component, the second source/drain region of the second pass transistor, and the gate electrode of the first latch transistor are electrically connected to one another; and

the first conductive member is electrically connected to an electrode selected from a group consisting of a V_SS electrode and a V_DD electrode.

3. The memory cell of claim 2, wherein:

the first source/drain region of the first pass transistor is electrically connected to a first bit line;

the first source/drain region of the second pass transistor is electrically connected to a second bit line;

the source regions of the first and second latch transistors are electrically connected to each other; and

the electrode sections of the first and second components are electrically connected to each other.

4. The memory cell of claim 2, wherein the second plates of the first and second capacitors and the first conductive member are electrically connected to one another.

5. The memory cell of claim 1, wherein:

the first transistor is a first pass transistor further including a first source/drain region and a second source/drain region;

the memory cell further comprises;

a second pass transistor having a first source/drain region, a second source/drain region, and a gate electrode having a first plate section;

a second capacitor having a first plate and a second plate, wherein;

the first plate includes the first plate section of the gate electrode of the second pass transistor;

the second plate includes a second conductive member; and

both plates of the second capacitor are substantially coincident with each other;

a first latch transistor having a source region, a drain region, and a gate electrode;

a second latch transistor having a source region, a drain region, and a gate electrode;

a first component having a storage node section and an electrode section, wherein the first component is selected from a group consisting of a resistor and a transistor; and

a second component having a storage node section and an electrode section, wherein the second component is selected from a group consisting of a resistor and a transistor; and

the memory cell is configured such that;

the first pass transistor, the first latch transistor, and the first component are associated with a first storage node;

the second pass transistor, the second latch transistor, and the second component are associated with a second storage node;

the drain region of the first latch transistor, the storage node section of the first component, the second source/drain region of the first pass transistor, and the gate electrode of the second latch transistor are electrically connected to one another; and

the drain region of the second latch transistor, the storage node section of the second component, the second source/drain region of the second pass transistor, and the gate electrode of the first latch transistor are electrically connected to one another.

6. The memory cell of claim 5, wherein:

the first source/drain region of the first pass transistor is electrically connected to a first bit line;

the first source/drain region of the second pass transistor is electrically connected to a second bit line;

the source regions of the first and second latch transistors are electrically connected to each other; and

the electrode sections of the first and second components are electrically connected to each other.

7. The memory cell of claim 6, further comprising:

a second capacitor having a first plate and a second plate, wherein;

the first plate of the second capacitor includes a first plate section of a gate electrode of a second transistor;

the second plate of the second capacitor overlies the first plate of the second capacitor;

the first and second plates of the second capacitor are substantially coincident with each other; and

the second capacitor is located within the memory cell; and

a second conductive member, wherein the second conductive member is electrically connected to;

the second plate of the second capacitor; and

a second region of the memory cell, wherein the second region is selected from a group consisting of a source/drain region, a source region, and a drain region,

wherein the memory cell is configured such that

the first conductive member is electrically connected to the first bit line; and

the second conductive member is electrically connected to the second bit line.

10. The memory cell of claim 1, further comprising a sidewall spacer, wherein:

the sidewall spacer lies between the first plate and the first conductive member;

the second plate has a first side and a second side that is opposite the first side;

the first side of the second plate is adjacent to the first plate;

the first conductive member contacts the second side of the second plate and the first region of the memory cell.

19. The memory cell of claim 1, wherein a first conductive member is electrically connected to an electrode selected from a group consisting of a V_SS electrode and a V_DD electrode.

20. The memory cell of claim 1, wherein a first conductive member is electrically connected to a bit line.

8. An integrated circuit including a static-random-access memory cell, wherein the integrated circuit comprises:

a substrate having a first region, a second region, and a third region, wherein the second region lies between and adjacent to the first and third regions;

a first capacitor comprising a first plate and a second plate, wherein;

the first plate of the first capacitor includes a first plate section of a gate electrode of a first latch transistor, and wherein the first plate of the first capacitor is disposed over the first region; and

the second plate of the first capacitor is disposed over and substantially coincident with the first plate of the first capacitor;

a second capacitor comprising a first plate and a second plate, wherein;

the first plate of the second capacitor includes a first plate section of a gate electrode of a second latch transistor, and wherein the first plate of the second capacitor is disposed over the third region; and

the second plate of the second capacitor is disposed over and substantially coincident with the first plate of the second capacitor; and

a first conductive member that is electrically connected to;

the second plates of the first and second capacitors;

the second region of the substrate; and

an electrode selected from a group consisting of a V_SS electrode and a V_DD electrode.

9. The integrated circuit of claim 8, wherein the circuit further comprises:

a first sidewall spacer adjacent to the first capacitor, the first conductive member, and the second region of the substrate; and

a second sidewall spacer adjacent to the second capacitor, the first conductive member, and the second region of the substrate.

21. The integrated circuit of claim 8, further comprising:

a fourth region, a fifth region, and a sixth region, wherein;

the fourth, fifth, and sixth regions lie within the substrate; and

the fifth region lies between and adjacent to the fourth and sixth regions;

a third capacitor comprising a first plate and a second plate, wherein;

the first plate of the third capacitor includes a portion of a first word line, and wherein the first plate of the third capacitor is disposed over the fourth region; and

the second plate of the third capacitor is disposed over and substantially coincident with the first plate of the third capacitor;

a fourth capacitor comprising a first plate and a second plate, wherein;

the first plate of the fourth capacitor includes a portion of a second word line, and wherein the first plate of the fourth capacitor is disposed over the sixth region; and

the second plate of the fourth capacitor is disposed over and substantially coincident with the first plate of the fourth capacitor; and

a second conductive member that is electrically connected to;

the second plates of the third and fourth capacitors;

the fifth region of the substrate; and

a bit line.

11. An integrated circuit including a first static-random-access memory cell and a second static-random-access memory cell, wherein the integrated circuit comprises:

a substrate having a first region, a second region, and a third region, wherein the second region lies between and adjacent to the first and third regions;

a first capacitor that lies within the first memory cell and includes a first plate and a second plate, wherein;

the first plate of the first capacitor includes a first plate section of a gate electrode of a first transistor of the first static-random-access memory cell, wherein the first plate of the first capacitor is disposed over the first region; and

the second plate of the first capacitor is disposed over and substantially coincident with the first plate of the first capacitor;

a second capacitor that lies within the second memory cell and includes a first plate and a second plate, wherein;

the first plate of the second capacitor includes a first plate of a gate electrode of a first transistor of the second static-random-access memory cell, wherein the first plate of the second capacitor is disposed over the third region; and

the second plate of the second capacitor is disposed over and substantially coincident with the first plate of the second capacitor; and

a first conductive member that is electrically connected to;

the second plates of the first and second capacitors;

the second region of the substrate; and

an electrode selected from a group consisting of a V_SS electrode and a V_DD electrode.

12. The integrated circuit of claim 11, wherein the first transistors are first latch transistors for the first and second static-random-access memory cells.

13. The integrated circuit of claim 11, further comprising:

a fourth region, a fifth region, and a sixth region, wherein;

the fourth, fifth, and sixth regions lie within the substrate; and

the fifth region lies between and adjacent to the fourth and sixth regions;

a third capacitor including a first plate and a second plate, wherein;

the first plate of the third capacitor includes a portion of a first word line, and wherein the first plate of the third capacitor is disposed over the third region; and

the second plate of the third capacitor is disposed over and substantially coincident with the first plate of the third capacitor;

a fourth capacitor including a first plate and a second plate, wherein;

the first plate of the fourth capacitor includes a portion of a second word line, and wherein the first plate of the fourth capacitor is disposed over the sixth region; and

the second plate of the fourth capacitor is disposed over and substantially coincident with the first plate of the fourth capacitor; and

a second conductive member that is electrically connected to;

the second plates of the third and fourth capacitors;

the fifth region of the substrate; and

a bit line.

14. The integrated circuit of claim 11, further comprising:

a first sidewall spacer adjacent to the first capacitor, the first conductive member, and the second region of the substrate; and

a second sidewall spacer adjacent to the second capacitor, the first conductive member, and the second region of the substrate.

15. The integrated circuit of claim 11, further comprising:

a fourth region, a fifth region, and a sixth region, wherein;

the fourth, fifth, and sixth regions lie within the substrate; and

the fifth region lies between and adjacent to the fourth and sixth regions;

a third capacitor that includes a first plate and a second plate, wherein;

the first plate of the third capacitor includes a first plate section of a gate electrode of a third transistor, wherein the first plate of the third capacitor is disposed over the fourth region of the substrate; and

the second plate of the third capacitor is disposed over and substantially coincident with the first plate of the third capacitor; and

a fourth capacitor that includes a first plate and a second plate, wherein;

the first plate of the fourth capacitor includes a first plate of a gate electrode of a fourth transistor, wherein the first plate of the fourth capacitor is disposed over the sixth region of the substrate; and

the second plate of the fourth capacitor is disposed over and substantially coincident with the first plate of the fourth capacitor,

wherein the first conductive member electrically connects the second plates of the first, second, third, and fourth capacitors, the second region of the substrate, and the fifth region of the substrate to one another.

16. The integrated circuit of claim 15, wherein the first, second, third, and fourth transistors are latch transistors.

17. The integrated circuit of claim 15, wherein the first conductive member contacts the second plates of the first, second, third, and fourth capacitors and the second region of the substrate.

18. The integrated circuit of claim 15, further comprising:

a first sidewall spacer adjacent to the first capacitor, the first conductive member, and the second region of the substrate; and

a second sidewall spacer adjacent to the second capacitor, the first conductive member, and the second region of the substrate.

22. An integrated circuit including a first static-random-access memory cell, a second static-random-access memory cell, and a third static-random-access memory cell, wherein the integrated circuit comprises:

a substrate having a first region, a second region, a third region, a fourth region, a fifth region, and a sixth region wherein;

the second region lies between and adjacent to the first and third regions; and

the fifth region lies between and adjacent to the fourth and sixth regions;

a first capacitor that lies within the first memory cell and includes a first plate and a second plate, wherein;

the first plate of the first capacitor includes a first plate section of a gate electrode of a first transistor of the first memory cell, wherein the first plate of the first capacitor is disposed over the first region;

the second plate of the first capacitor is disposed over and substantially coincident with the first plate of the first capacitor;

a second capacitor that lies within the second memory cell and includes a first plate and a second plate, wherein;

the first plate of the second capacitor includes a first plate of a gate electrode of a transistor of the second memory cell, wherein the first plate of the second capacitor is disposed over the third region; and

the second plate of the second capacitor is disposed over and substantially coincident with the first plate of the second capacitor;

a third capacitor that lies within the first memory cell and includes a first plate and a second plate, wherein;

the first plate of the third capacitor includes a first plate section of a gate electrode of a second transistor of the first memory cell, wherein the first plate of the third capacitor is disposed over a fourth region of the substrate; and

the second plate of the third capacitor is disposed over and substantially coincident with the first plate of the third capacitor;

a fourth capacitor that lies within the third memory cell and includes a first plate and a second plate, wherein;

the first plate of the fourth capacitor includes a first plate of a gate electrode of a transistor of the third memory cell, wherein the first plate of the fourth capacitor is disposed over a sixth region of the substrate; and

the second plate of the fourth capacitor is disposed over and substantially coincident with the first plate of the fourth capacitor; and

a conductive member that is electrically connected to the second plates of the first, second, third, and fourth capacitors, and the second region of the substrate, and the fifth region of the substrate.

23. The integrated circuit of claim 22, wherein the first and second transistors of the first memory cell, and the transistors of the second and third memory cells are latch transistors.

24. The integrated circuit of claim 22, further comprising:

a first sidewall spacer adjacent to the first capacitor, the conductive member, and the second region of the substrate;

a second sidewall spacer adjacent to the second capacitor, the conductive member, and the second region of the substrate;

a third sidewall spacer adjacent to the third capacitor, the conductive member, and the fifth region of the substrate; and

a fourth sidewall spacer adjacent to the fourth capacitor, the conductive member, and the fifth region of the substrate.

25. The integrated circuit of claim 22, wherein the conductive member is electrically connected to a V_SS electrode.