Antifuse-based programmable logic circuit

• US 5,486,776 A
• Filed: 09/29/1994
• Issued: 01/23/1996
• Est. Priority Date: 09/29/1994
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Chiang, David
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/315,009
• Time in Patent Office: 481 Days
• Field of Search: 326/38-39, 326/41, 326/101, 327/525, 365/96, 365/104, 365/105, 365/225.7, 257/50, 257/530
• US Class Current: 326/41
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns

Abstract

A programmable interconnect is provided that includes a first plurality of lines, a second plurality of lines, and means for connecting one of the first plurality of lines to one of the second plurality of lines, wherein the means for connecting includes an antifuse and a diode. The diode in this configuration performs the equivalent logical function as an AND gate. Programing the antifuse determines the diode-AND gate function performed. In this manner, a programmable interconnect array in accordance with the present invention, formed using standard fabrication processes, provides an area-efficient implementation of a wide AND functionality.

Claims

1. A programmable logic circuit comprising:

a first plurality of lines;

a second plurality of lines;

means for connecting at least one of said first plurality of lines to at least one of said second plurality of lines, wherein said means for connecting includes an antifuse and a diode connected in series, wherein said antifuse is formed over a diffusion area in a well area, and said diode is formed from said diffusion area and said well area.

2. The programmable interconnect of claim 1 wherein the anode of said diode is coupled to said antifuse and the cathode of said diode is coupled to said one of said first plurality of lines.

3. The programmable interconnect of claim 2 wherein said antifuse is further coupled to said one of said second plurality of lines.

4. The programmable interconnect of claim 3 further comprising a resistance coupled to said one of said second plurality of lines.

5. The programmable interconnect of claim 4 further comprising a voltage source coupled to said resistance.

6. A method for providing a wide fan-in functionality comprising the steps of:

interconnecting two sets of conductive lines with programmable means, wherein said programmable means includes a diode and an antifuse connected in series, wherein said antifuse is formed over a diffusion area in a well area, and said diode is formed from said diffusion area and said well area.