Wireless direct-sequence spread spectrum TDMA communications system
First Claim
1. A method of direct-sequence spread spectrum (DSSS) digital communication between a transmitter and a receiver within a frequency band including a predetermined lower limit frequency, a predetermined center frequency, and a predetermined upper limit frequency, said method at the transmitter comprising the steps of:
- generating continuously and repetitively at a predetermined chip-clock rate about one-half of the predetermined frequency bandwidth, a pseudorandom digital sequence (PRDS) code comprising a multiplicity of bits and having a bit sequence length equal to the product of a first integer and a second integer, each complete sequence of the code generated over a predetermined time interval;
intermittently modulating onto the PRDS code, in accordance with protocol for repetitively determining whether, when, and over what duration the transmitter may transmit, the protocol common to the transmitter and the receiver, a plurality of data signals, each signal comprising a plurality of digital symbols, wherein the number of chips encoding a symbol is a third integer, the number of bits included in a symbol is a fourth integer, and the number of bits included in a digital byte is a fifth integer;
intermittently transmitting the data-modulated PRDS code, each transmission of a code segment beginning at a time determined by the protocol and initialized at a preselected and identifiable bit position in the PRDS code, the bit position selected from among the multiplicity of bits comprising the code, each transmission comprising a predetermined number of data bytes and terminating at a time determined by the protocol, each transmission beginning and ending at a position in the PRDS code coinciding with one of a multiplicity of symbol boundaries;
transmitting each transmission of the data-modulated PRDS code at a signal center frequency about equal to the center frequency of the frequency band;
said method at the receiver comprising the steps of;
generating continuously and repetitively, at the chip-clock rate of the transmitter PRDS code, a PRDS code identical to the transmitter PRDS code, each complete sequence of the receiver-generated code generated over said predetermined time interval;
receiving from the transmitter, when the transmitter is transmitting, the data-modulated PRDS code;
synchronizing a bit sequence in the receiver-generated PRDS code with a corresponding bit sequence in the transmitter PRDS code segment;
demodulating the data signals modulated onto the received code segment.
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Accused Products
Abstract
A protocol for wireless direct user-to-user DSSS TDMA digital communication at a data rate of the order of one to several megabits per second in the 902-928 MHz, 2400-2483.5 MHz or 5725-5850 MHz band includes a sequence of transactions, each transaction consisting of a predetermined sequence of subpackets, and each subpacket consisting of a predetermined number of bytes preallocated to a subpacket element or element portion. Network communications among a plurality of stationary and/or mobile users such as personal computers, each equipped with a (Remote Unit) transceiver, are organized and directed by a Master Unit transceiver. Master Unit and Remote Unit transceivers have identical circuitry. Using a first pseudorandom code sequence (M-code), the Master Unit intermittently transmits a DSSS signal enabling Remote Units to synchronize to the Master Unit and so receive scheduling directives. A Remote Unit, while maintaining synchronization with the Master Unit, sends information by transmitting a DSSS signal using a second pseudorandom code sequence (R-code). To facilitate synchronization, the Master Unit also transmits a continuously running DSSS signal using a third pseudorandom code sequence (P-code) which is code-locked and phase-locked to the M-code. A transceiver implementing the protocol in the 2400-2483.5 MHz band includes a microprocessor, external data RAM, Control Logic Section, Analog Section, and Radiofrequency Section.
248 Citations
39 Claims
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1. A method of direct-sequence spread spectrum (DSSS) digital communication between a transmitter and a receiver within a frequency band including a predetermined lower limit frequency, a predetermined center frequency, and a predetermined upper limit frequency, said method at the transmitter comprising the steps of:
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generating continuously and repetitively at a predetermined chip-clock rate about one-half of the predetermined frequency bandwidth, a pseudorandom digital sequence (PRDS) code comprising a multiplicity of bits and having a bit sequence length equal to the product of a first integer and a second integer, each complete sequence of the code generated over a predetermined time interval; intermittently modulating onto the PRDS code, in accordance with protocol for repetitively determining whether, when, and over what duration the transmitter may transmit, the protocol common to the transmitter and the receiver, a plurality of data signals, each signal comprising a plurality of digital symbols, wherein the number of chips encoding a symbol is a third integer, the number of bits included in a symbol is a fourth integer, and the number of bits included in a digital byte is a fifth integer; intermittently transmitting the data-modulated PRDS code, each transmission of a code segment beginning at a time determined by the protocol and initialized at a preselected and identifiable bit position in the PRDS code, the bit position selected from among the multiplicity of bits comprising the code, each transmission comprising a predetermined number of data bytes and terminating at a time determined by the protocol, each transmission beginning and ending at a position in the PRDS code coinciding with one of a multiplicity of symbol boundaries; transmitting each transmission of the data-modulated PRDS code at a signal center frequency about equal to the center frequency of the frequency band; said method at the receiver comprising the steps of; generating continuously and repetitively, at the chip-clock rate of the transmitter PRDS code, a PRDS code identical to the transmitter PRDS code, each complete sequence of the receiver-generated code generated over said predetermined time interval; receiving from the transmitter, when the transmitter is transmitting, the data-modulated PRDS code; synchronizing a bit sequence in the receiver-generated PRDS code with a corresponding bit sequence in the transmitter PRDS code segment; demodulating the data signals modulated onto the received code segment. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of DSSS time-division multiple access (TDMA) digital communication between a first transceiver comprising a first transmitter and a first receiver and a second transceiver comprising a second transmitter and a second receiver, within a frequency band including a predetermined lower limit frequency, a predetermined center frequency, and a predetermined upper limit frequency, said method at the first transmitter comprising the steps of:
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generating continuously and repetitively at a predetermined chip-clock rate about one-half of the predetermined frequency bandwidth, a first PRDS code comprising a first multiplicity of bits and having a bit sequence length equal to the product of a first integer and a second integer, each complete sequence of the first code generated over a predetermined time interval; intermittently modulating onto the first PRDS code, in accordance with a protocol for repetitively determining whether, when, and over what duration the first transmitter or the second transmitter may transmit, the protocol common to the first transmitter, second receiver second transmitter, and first receiver, a plurality of data signals, each signal comprising a plurality of digital symbols, wherein the number of chips encoding a symbol is a third integer, the number of bits included in a symbol is a fourth integer, and the number of bits included in a digital byte is a fifth integer; intermittently transmitting the data-modulated first PRDS code, each transmission of a code segment beginning at a time determined by the protocol and initialized at a preselected and identifiable bit position in the first PRDS code, the bit position selected from among the multiplicity of bits comprising the code, each transmission comprising a predetermined number of symbols and terminating at a time determined by the protocol, each transmission beginning and ending at a position in the first PRDS code coinciding with one of a multiplicity of symbol boundaries; transmitting each transmission of the data-modulated first PRDS code at a signal center frequency about equal to the center frequency of the frequency band; said method at the second receiver comprising the steps of; generating continuously and repetitively, at the chip-clock rate of the first transmitter first PRDS code, a PRDS code identical to the first transmitter first PRDS code, each complete sequence of the receiver-generated code generated over said predetermined time interval; receiving from the first transmitter, when the first transmiter is transmitting, the data-modulated first PRDS code; synchronizing a bit sequence in the receiver-generated PRDS code with a corresponding bit sequence in the first transmitter first PRDS code segment; demodulating the data signals modulated onto the received code segment; said method at the second transmitter comprising the steps of; generating continuously and repetitively at said predetermined chip-clock rate, a second PRDS code having a sequence length equal to the product of said first integer and said second integer, each complete sequence of the second code generated over said predetermined time interval; intermittently modulating onto the second PRDS code, in accordance with the protocol, a plurality of data signals, each signal comprising a plurality of digital symbols, wherein the number of chips encoding a symbol is said third integer, the number of bits included in a symbol is said fourth integer, and the number of bits included in a digital byte is said fifth integer; intermittently transmitting the data-modulated second PRDS code, each transmission of a code segment beginning at a time determined by the protocol and initialized at a preselected and identifiable bit position in the second PRDS code, the bit position selected from among the multiplicity of bits comprising the code, each transmission comprising a predetermined number of data bytes and terminating at a time determined by the protocol, each transmission beginning and ending at a position in the second PRDS code coinciding with one of a multiplicity of symbol boundaries; transmitting each transmission of the data-modulated second PRDS code at a signal center frequency about equal to the center frequency of the frequency band; said method at the first receiver comprising the steps of; generating continuously and repetitively at said chip-clock rate a PRDS code identical to the second PRDS code generated by the second transmitter, each complete sequence of the receiver-generated code generated over said predetermined time interval; receiving from the second transmitter, when the second transmitter is transmitting, the data-modulated second PRDS code; synchronizing a bit sequence in the receiver-generated PRDS code with a corresponding bit sequence in the second transmitter PRDS code segment; demodulating the data signals modulated onto the received code segment. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of DSSS TDMA digital communication within a network via a communication medium, the network comprising a Master Unit (MU) transceiver comprising a transmitter and a receiver, and a plurality of Remote Unit (RU) transceivers identical to the MU transceiver, said method comprising executing a plurality of sequential communication transactions, each transaction comprising
transmitting, using a first PRDS code, a first type of subpacket from the MU to at least one RU; -
receiving at the RU(s) the subpacket transmitted from the MU; transmitting, using a second PRDS code, at least one subpacket from at least one RU; receiving at the MU and at least one RU each subpacket transmitted from an RU. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A DSSS TDMA network operating over a predetermined region within a frequency band including a predetermined lower limit frequency and a predetermined upper limit frequency, the network comprising:
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a Master Unit node comprising a transceiver communicating via a communication medium, the transceiver comprising a radiofrequency portion and an analog portion, the radiofrequency portion comprising a data transmitter and at least one receiver, the analog portion comprising a master clock, the MU transceiver transmitting or receiving in accordance with a protocol for repetitively determining whether, when, and over what duration a network transceiver may transmit; a plurality of Remote Unit nodes associated with the MU node, each RU node comprising a transceiver identical to the MU transceiver and communicating via said communication medium, each RU transceiver, when transmitting, transmitting in accordance with the protocol, each RU transceiver, when receiving, receiving in accordance with the protocol; first link means for establishing a direct communication link from the MU to all RU'"'"'s in the network; second link means for establishing a direct communication link from an RU to the MU; and third link means for establishing a direct communication link from a first RU designated by the MU as a Remote Unit Initiator (RUI) to a second RU selected by the first RU and designated by the MU as a Remote Unit Recipient (RUR). - View Dependent Claims (32, 33, 34, 35, 36)
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37. A device for wireless transmission and reception of DSSS TDMA digital signals within a frequency band including a predetermined lower limit frequency and a predetermined upper limit frequency, the device comprising a radiofrequency portion comprising:
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a frequency generator generating continuously and repetitively at a first predetermined chip-clock rate about one-half the predetermined frequency bandwidth, a first PRDS code having a bit sequence length equal to the product of a first integer and a second integer, each complete sequence of the first code generated over a predetermined time interval, the frequency generator further generating continuously and repetitively at a second predetermined chip-clock rate evenly divisible into the first chip-clock rate by a factor which is a third integer, a second PRDS code having a bit sequence length equal to a fourth integer, each complete sequence of the second code generated over said predetermined time interval, each successive chip of the second PRDS code being in a predetermined one-to-one correspondence with a chip which is the leading chip of the chips comprising successive bits in the first PRDS code and separated by a number of chips equal to a fifth integer, a preselected and identifiable position in the first PRDS code being permanently aligned with a preselected and identifiable position in the second PRDS code; a pilot signal transmitter continuously transmitting the second PRDS code at a signal center frequency near a limit frequency of the frequency band; and a data signal transmitter intermittently transmitting a data-modulated first PRDS code signal at a signal center frequency near the center frequency of the frequency band. - View Dependent Claims (38, 39)
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Specification