Circuits, systems and methods for improving page accesses and block transfers in a memory system

CAFC
  • US 5,500,819 A
  • Filed: 09/30/1994
  • Issued: 03/19/1996
  • Est. Priority Date: 09/30/1994
  • Status: Expired due to Term
First Claim
Patent Images

1. A memory comprising:

  • an array of rows and columns of volatile memory cells;

    addressing circuitry for providing access to selected ones of said memory cells;

    master read/write circuitry for reading and writing data into said selected ones of said cells;

    first slave circuitry for storing data for exchange with said master read/write circuitry;

    second slave circuitry for storing data for exchange with said master read/write circuitry; and

    control circuitry for controlling exchange of data between said master read/write circuitry and said first and second slave circuitry, said control circuitry operable during a move operation to;

    control sensing by said master read/write circuitry of data from a said row in said array selected by said addressing circuitry;

    control transfer of said data from said master read/write circuitry to a selected one of said first and second slave circuitry; and

    control writing of said data through said master read/write circuitry to a second said row in said array selected by said addressing circuitry.

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