Semiconductor device structure including multiple interconnection layers with interlayer insulating films

• US 5,502,337 A
• Filed: 11/18/1994
• Issued: 03/26/1996
• Est. Priority Date: 07/04/1994
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nozaki, Masahiko
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/344,572
• Time in Patent Office: 494 Days
• Field of Search: 257/773, 257/775, 257/786, 257/774
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05095 at the periphery of the internal layers
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

The present invention relates to a bonding pad electrode structure having sufficiently large allowable current and improved to prevent generation of cracks in an interlayer insulating film by mechanical stress at the time of wire bonding. Interlayer insulating films are provided directly on a semiconductor substrate. An uppermost interconnection layer is provided on interlayer insulating films. Since a lower interconnection layer does not exist immediately below a portion of the uppermost interconnection layer used as a bonding pad, cracks are not generated in the interlayer insulating films at the time of wire bonding. Further, since the uppermost interconnection layer is connected to lower interconnection layers, the current entering the bonding pad is dispersed to these interconnection layers.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a circuit provided on said semiconductor substrate;

a wire bonding portion provided apart from said circuit on said semiconductor substrate; and

a drawing line portion provided on said semiconductor substrate for connecting said wire bonding portion and said circuit;

wherein

said wire bonding portion includes first, second and third interlayer insulating films provided directly on said semiconductor substrate, and an uppermost interconnection layer provided directly on said first, second and third interlayer insulating films; and

said drawing line portion includes

(1) a first insulating film provided on said semiconductor substrate,

(2) a first lower interconnection layer provided on said first insulating film,

(3) a second insulating film provided on said first insulating film to cover said first lower interconnection layer,

(4) a second lower interconnection layer provided so as to overlap with said first lower interconnection layer with said second insulating film therebetween,

(5) a third insulating film provided on said second insulating film to cover said second lower interconnection layer,

(6) said uppermost interconnection layer provided so as to overlap with said second lower interconnection layer with said third insulating film therebetween,

a first via hole provided in said second insulating film;

a first conductive material filled in said first via hole for electrically connecting said first lower interconnection layer and said second lower interconnection layer;

a second via hole provided in said third insulating film;

a second conductive material filled in said second via hole for electrically connecting said uppermost interconnection layer and said second lower interconnection layer.

2. The semiconductor device according to claim 1, wherein

said second lower interconnection layer is a second interconnection layer counting from said uppermost interconnection layer.

3. The semiconductor device according to claim 1, wherein said first lower interconnection layer is a third interconnection layer counting from said uppermost interconnection layer.

4. A semiconductor device, comprising:

a semiconductor substrate;

an annular lower interconnection layer provided on said semiconductor substrate with a space at the center;

an interlayer insulating film provided on said semiconductor substrate to fill said space and to cover said lower interconnection layer;

an uppermost interconnection layer provided on said interlayer insulating film to cover said space and to cover said lower interconnection layer;

a via hole provided in said interlayer insulating film for connecting said annular lower interconnection layer and said uppermost interconnection layer; and

a conductive material filled in said via hole for electrically connecting said lower interconnection layer and said uppermost interconnection layer;

wherein

a portion of said uppermost interconnection layer positioned above said space is used as a bonding pad.

5. The semiconductor device according to claim 4, wherein

said lower interconnection layer is a second interconnection layer counting from said uppermost interconnection layer.

6. The semiconductor device according to claim 4, wherein

a plurality of said via holes are provided in said interlayer insulating film so as to surround said bonding pad.