System and method for remote identification of coded articles and the like

• US 5,502,445 A
• Filed: 05/22/1995
• Issued: 03/26/1996
• Est. Priority Date: 12/29/1992
• Status: Expired due to Term

• Current Assignee: Sarnoff Corporation (SRI International, Inc.)
• Original Assignee: David Sarnoff Research Center, Inc.
• Inventors: Schepps, Jonathan L., Dingwall, Andrew G. F.
• Primary Examiner(s): Hellner, Mark
• Application Number:
  US08/445,641
• Time in Patent Office: 309 Days
• Field of Search: 342/51, 342/44, 329/311, 329/312, 375/25, 375/7, 375/94
• US Class Current: 342/51
• CPC Class Codes: G01S 13/76 wherein pulse-type signals are transmitted
• CPC Class Codes: G01S 13/765 with exchange of information between interrogator and responder
• CPC Class Codes: G01S 13/767 Responders; Transponders teaching or practice apparatus for gun-aiming or gun-laying using reflecting targets or active targets F41G3/26
• CPC Class Codes: G01S 13/78 discriminating between different kinds of targets, e.g. IFF-radar, i.e. identification of friend or foe G01S13/75, G01S13/79 take precedence
• CPC Class Codes: G07C 9/28 the pass enabling tracking or indicating presence

Abstract

There is described an electronic interrogation and identification (I/I) system in which an interrogator/reader (I/R) unit operates remotely using a microwave beam in conjunction with one or more coded articles. The articles are identified by a unique method and search sequence. As the I/R unit interrogates the articles, one or more of them respond to the I/R unit whenever a code word (data value) sent from the I/R unit matches a code word stored in one or more of the memory positions within the articles. After searching through all of the possible code words and word positions the I/R unit will have identified at least one code word stored in each of the word positions of at least one article. Then combinations of the just-identified code words are matched with the respective stored words of the various articles. After being uniquely identified each article is "powered-down" on command from the I/R unit and remains inactive so that one-by-one all remaining articles are also identified.

Claims

1. A circuit for receiving and responding to digital bit signals, the circuit comprising:

an input stage comprising first and second MOS detector transistors each having a gate, a source and a drain with their gates connected in common to the drain of the first transistor, the sources of the transistors being connected respectively to a first rail and to an input terminal for receiving the digital bit signals;

first and second MOS transistors connected as controlled current sources respectively to the drains of the first and second detector transistors,

a first small capacitor connected between the drain of the first detector transistor and the first rail,

a second capacitor connected between the drain of the second detector transistor and the first rail, the voltage across the second capacitor in the absence of an incoming signal being substantially different from the voltage across the first capacitor; and

at least one amplifier stage of a p-channel field effect transistor (FET) and an n-channel FET series connected with common gate input and common drain output, the common gate input of the stage being connected in parallel with the second small capacitor, the output of the amplifier stage switching between the first rail and a second rail potential when the voltage across the second capacitor changes sufficiently in response to the microwave signal such that the output of the amplifier stage produces binary "0" and "1" bits in accordance with the signals.

2. The circuit of claim 1 wherein the first and second detector transistors are n-channel FETs, and the first and second current supply transistors are p-channel FETs, and the first rail is at ground potential.

3. The circuit of claim 1 wherein the first and second detector transistors each have a gate width of roughly 40 microns and are closely matched to each other, the first and second capacitors are stray capacitances, and the current through the second detector transistor is somewhat higher than that through the first detector transistor.

4. The circuit of claim 1 wherein the n-channel FET and p-channel FET of the amplifier stage have gate widths much narrower than the gate widths of the first and second detector transistors.

5. The circuit of claim 1 in further combination with switchable current supply means for supplying additional current to the second detector transistor, the switchable current supply means being actuated by the binary bits outputted from the amplifier stage such that the efficiency of the input stage is enhanced.

6. The circuit of claim 1 in further combination with means for generating clock pulses, each clock pulse occurring after a binary "0" and during a binary "1" from the amplifier stage.

7. The circuit of claim 6 further comprising a reset unit for placing the circuit in quiescent state when there is no signal, and for enabling the circuit to active state when there is a signal, the reset unit being connected to receive binary "0" and "1" bits and on receipt of a given plurality of consecutive "1" bits enabling the circuit to active state, and for generating a synchronizing pulse to insure the accurate framing of the binary bits into proper sequences of words.

8. The circuit of claim 7 further comprising:

memory, logic and control means for storing coded information in the form of binary words and for comparing the stored words with words received via the signals; and

signalling means for generating response signals when the stored and received words match.

9. A metal oxide semiconductor (MOS) detector for signals comprising:

first and second MOS transistors connected as a common-gate source-driven amplifier with the gates of the two transistors being connected to the drain of the first transistor, the source of the first transistor being connected to a first voltage rail, the source of the second transistor being connected to an input for the signals;

first and second controlled current sources for supplying unequal currents to the first and second MOS transistors;

a first capacitor connected between the drain of the first transistor and the first rail; and

a second capacitor connected between the drain of the second transistor and the first rail, the voltage on the second capacitor having a quiescent value in the absence of a signal, the voltage on the second capacitor being incrementally changed a slight amount by each cycle of the signal thereby substantially changing the voltage after a sufficient number of cycles of the signal.

10. The detector of claim 9 wherein the first and second transistors are each n-channel FETs and are closely matched, the first and second current sources being first and second p-channel FETs controlled by a current mirror arrangement.

11. The detector of claim 10 further comprising:

an amplifier stage comprising a p-channel FET and an n-channel FET connected as an inverter amplifier with common gates connected to the second capacitor, and common drains connected to an output lead such that when the voltage on the second capacitor changes sufficiently from its quiescent value, the output lead is switched in polarity.

12. The detector of claim 11 wherein the gates of the first and second n-channel FET s of the detector are about 40 microns wide and the gates of the transistors of the amplifier stage are only about 3 microns wide.

13. The detector of claim 11 further comprising voltage switching means for supplying the amplifier stage with a voltage from a second voltage rail, the voltage to the amplifier stage being reduced when there is no signal and being increased to the second rail potential after a signal is present.