Electrical interconnect using particle enhanced joining of metal surfaces

• US 5,506,514 A
• Filed: 04/12/1995
• Issued: 04/09/1996
• Est. Priority Date: 02/14/1990
• Status: Expired due to Term

• Current Assignee: Bio Lab Naturals, Inc. (Limitless X Holdings, Inc.)
• Original Assignee: Particle Interconnect, Inc. (China Crescent Enterprises, Inc.)
• Inventors: Difrancesco, Louis
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): BOWSER, BARRY
• Application Number:
  US08/422,546
• Time in Patent Office: 363 Days
• Field of Search: 428/1, 29/846, 361/785, 361/760-764, 361/792, 361/803, 174/260, 174/261, 439/44, 439/65-66, 439/74
• US Class Current: 324/754.2
• CPC Class Codes: B23K 20/16 with interposition of special material to facilitate connection of the parts, e.g. material for absorbing or producing gas
• CPC Class Codes: B23K 35/02 characterised by mechanical features, e.g. shape
• CPC Class Codes: H01H 1/06 characterised by the shape or structure of the contact-making surface, e.g. grooved
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 3/325 by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor adaptations of leads inserted in holes for press-fit connections H05K3/308
• CPC Class Codes: H05K 3/328 by welding
• CPC Class Codes: H05K 3/4007 Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: Y10S 428/929 : Electrical contact feature
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 428/12486 : Laterally noncoextensive components [e.g., embedded, etc.]
• CPC Class Codes: Y10T 428/24999 : Inorganic

Abstract

A method and apparatus for electrically interconnecting various electronic elements, including circuit components, assemblies, and subassemblies. A particle enhanced material metal contact layer, having a surface, formed on the electronic elements, includes particles of greater hardness disposed on and/or within the metal contact layer, which particles form protuberances that concentrate stress when said contact surface is brought into contact with an opposing surface under pressure, to thereby penetrate the opposing surface and form a metal matrix between the two surfaces. The invention includes preferred and alternative embodiments incorporating particle enhanced material that provide a semiconductor test array which may be patterned as desired to receive an integrated circuit die and/or packaged components to facilitate integrated circuit and packaged electronic component testing; a probing device for testing integrated circuit die in situ on a semiconductor wafer; connectors for coupling discontinuous circuit element substrates; an interposer for interconnecting conventional components, circuit boards, and assemblies; and connectors for single and multiple layer circuit boards.

Claims

1. An apparatus for testing at least one integrated circuit in situ on a silicon wafer, comprising:

a probe array having individual interconnect elements for contacting corresponding terminal pads on said integrated circuit, each interconnect element of said probe array having a metal contact layer, including associated particles having a hardness greater than that of said metal; and

means for applying compressive force normal to said probe array and said integrated circuit;

whereby a conductive metal matrix is formed between each of said probe array interconnect elements and a corresponding terminal pad when said particles pierce a terminal pad surface.