Method of interconnect in an integrated circuit

• US 5,510,298 A
• Filed: 09/12/1994
• Issued: 04/23/1996
• Est. Priority Date: 09/12/1991
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Redwine, Donald J.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/304,628
• Time in Patent Office: 589 Days
• Field of Search: 437/203, 437/192, 437/245, 257/767, 257/773, 257/776, 257/970, 257/758, 257/763
• US Class Current: 438/622
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit interconnect structure is provided, along with a method of forming the integrated circuit interconnect structure. A semiconductor material layer has an elongate trench formed therein. A conducting region is disposed in the trench. An insulator region overlies the conducting region. One or more contact regions are disposed through the insulator region to contact the conducting region.

Claims

1. A method of forming an integrated circuit interconnect structure, said method comprising the steps of:

forming first and second elongate trenches in a semiconductor substrate layer;

forming a conducting region in each of said first and second elongate trenches to form a first conducting region and a second conducting region;

forming an insulator region overlying each said conducting region, said first and second conducting regions adapted for conduction of current parallel to said insulator regions;

forming a first and a second conducting line overlying said insulator region, said first and said second conducting line are parallel to said first and said conducting regions respectively; and

forming two or more contact regions through each of said insulator regions to couple electrically in parallel said first conducting region with said first conducting line and to couple electrically said second conducting region with said second conducting line.

2. The method of claim 1 and further comprising the step of forming said first and second elongate trenches to have a depth of at least four times their widths.

3. The method of claim 1 wherein said conducting line forming step comprises the step of forming a portion of said conducting line perpendicular to a portion of said trench.

4. The method of claim 1 and further comprising the step of forming a second insulator region in said trench between said semiconductor material and said conducting regions.

5. A method of forming an integrated circuit interconnect structure, said method comprising the steps of:

forming plural elongate trenches in a semiconductor material layer;

forming a conducting region in each of said elongate trenches;

forming a first insulator region overlying each said conducting region in said trenches, wherein said conducting region in each of said elongate trenches is adapted for conduction of current parallel to said first insulator region;

forming a second insulator region in each of said elongate trenches between said semiconductor material and said conducting region;

forming one or more conducting lines overlying said first insulator region overlying each said conducting region; and

forming at least two contact regions through said first insulator region overlying each said conducting region to connect electrically in parallel each said conducting region to at least one said conducting line.

6. The method of claim 5 wherein said forming an elongate trench step includes the step of forming said elongate trench such that a depth of said elongate trenches is at least four times deeper than a width of said elongate trenches.

7. The method of claim 5 wherein said conducting line forming step comprises the step of forming said conducting line substantially parallel to said trench.

8. The method of claim 5 wherein said conducting line forming step comprises the step of forming a portion of said conducting line substantially perpendicular to said trench.

9. A method of controlling the frequency response of a conducting strip of an interconnect structure, said method comprising the steps of:

forming a metal line in a semiconductor material layer;

forming an insulating layer over said metal line;

forming at least one conducting via in said insulating layer, said conducting via being electrically coupled to said metal line by a plurality of conducting contacts;

forming said conducting strip on said insulating layer, said conducting strip being coupled in parallel electrically to said conducting via.

10. The method of claim 9 further including the step of using said semiconductor material layer to isolate capacitively said metal line from another metal line formed in said semiconductor material.

11. The method of claim 9 wherein said forming a metal line step includes the step of fabricating a depth dimension for said metal line greater than a width dimension.

12. The method of claim 9 wherein said forming a metal line step includes a step of forming said metal line parallel to said conducting strip.