Non-volatile semiconductor memory device and method for manufacturing the same

• US 5,514,889 A
• Filed: 08/18/1993
• Issued: 05/07/1996
• Est. Priority Date: 08/18/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Myoung-kwan, Choi, Jeoug-hyuk
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/107,901
• Time in Patent Office: 993 Days
• Field of Search: 257/316, 257/371, 257/548, 257/324
• US Class Current: 257/316
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

An EEPROM device in which a high voltage is applied to the chip during the memory cell operation and a method for the manufacturing the same are disclosed. On a P-type semiconductor substrate, a first N-well is formed in a surface portion of the substrate in the cell array region and a second N-well is formed in a first surface of the substrate in the peripheral circuit region. An EEPROM memory cell is formed on the first P-well and a first NMOS transistor is formed on the second P-well. Also, a second NMOS transistor is formed on a second surface portion of the semiconductor substrate in the peripheral circuit 10 region and a PMOS transistor is formed on the second N-well. The impurity concentrations of the first and second P-wells are controlled in accordance with the characteristic of the MOS transistors to be formed. Further, a second NMOS transistor having a resistance against a high voltage is directly formed on the P-type substrate. Thus, the electric characteristic of the EEPROM device is enhanced.

Claims

1. An EEPROM semiconductor memory device comprising:

a semiconductor substrate having a first conductivity type, said semiconductor substrate being divided into a cell array region and a peripheral circuit region;

a first impurity-doped region having said first conductivity type formed in a first surface portion of said semiconductor substrate in said cell array region;

a second impurity-doped region having a second conductivity type formed in said first surface portion of said semiconductor substrate in said cell array region, said second impurity-doped region enclosing said first impurity-doped region;

a memory cell comprising;

a memory source region and a memory drain region formed on a surface portion of said first impurity-doped region, and

a floating electrode formed on said first impurity-doped region and a control electrode formed on said floating electrode;

a third impurity-doped region having said first conductivity type formed in a first surface portion in said peripheral circuit region of said semiconductor substrate;

a first MOS transistor comprising;

first source and drain regions formed in respective surface portions of said third impurity-doped region, and

a first gate electrode formed on said third impurity-doped region;

a second MOS transistor comprising;

second source and drain regions formed directly in respective second surface portions in said peripheral circuit region of said semiconductor substrate, and

a second gate electrode formed on said semiconductor substrate;

a fourth impurity-doped region having said second conductivity type and being formed in a third surface portion in said peripheral circuit region of said semiconductor substrate; and

a third MOS transistor comprising;

third source and drain regions formed in respective surface portions of said fourth impurity-doped region, and

a third gate electrode formed on said fourth impurity-doped region.

2. The EEPROM semiconductor memory device according to claim 1, wherein said first and second MOS transistors are NMOS transistors, and said third MOS transistor is a PMOS transistor.

3. The EEPROM semiconductor memory device according to claim 1, wherein a first gate insulating film of said second MOS transistor is thicker than a second gate insulating film of said first MOS transistor.

4. The EEPROM semiconductor memory device according to claim 1, wherein said second MOS transistor is formed between said first MOS transistor and said third MOS transistor.

5. The EEPROM semiconductor memory device according to claim 1, wherein a first impurity concentration of said first impurity-doped region is controlled independently from a second impurity concentration of said third impurity-doped region.

6. The EEPROM semiconductor memory device according to claim 1, wherein said first conductivity type is P-type and said second conductivity type is N-type.

9. The EEPROM semiconductor memory device according to claim 1, wherein said first impurity-doped region and said third impurity-doped region are formed substantially simultaneously, and said second impurity-doped region and said fourth impurity-doped region are formed substantially independently.

7. An EEPROM semiconductor memory device comprising:

a P-type semiconductor substrate which is divided into a cell array region and a peripheral circuit region;

a first P-well formed in a surface portion in said cell array region of said semiconductor substrate;

a first N-well formed in said surface portion in said cell array region of said semiconductor substrate, said first N-well enclosing said first P-well;

a memory cell comprising;

a memory source region and a memory drain region formed on a surface portion of said first P-well,

a floating electrode formed on said first P-well, and

a control electrode formed over said floating electrode;

a second P-well formed in a first surface portion of said peripheral circuit region of said semiconductor substrate;

a first NMOS transistor comprising;

first source and drain regions formed in respective surface portions of said second P-well, and

a first gate electrode formed on said second P-well;

a second NMOS transistor comprising;

second source and drain regions formed directly in a second surface portion of said peripheral circuit region of said semiconductor substrate, and

a second gate electrode formed on said second surface portion of said peripheral circuit region of said semiconductor substrate;

a second N-well formed in a third surface portion of said peripheral circuit region of said semiconductor substrate; and

a PMOS transistor comprising;

third source and drain regions formed in a surface portion of said second N-well, and

a third gate electrode formed on said second N-well.

8. The EEPROM semiconductor memory device according to claim 7, wherein said first N-well and said second N-well are formed substantially simultaneously, and said first P-well and said second P-well are formed substantially independently.