Apparatus and method for clock alignment and switching

• US 5,515,403 A
• Filed: 06/21/1994
• Issued: 05/07/1996
• Est. Priority Date: 06/21/1994
• Status: Expired due to Term

• Current Assignee: Alcatel-Lucent USA, Inc. (Nokia Corporation)
• Original Assignee: DSC Communications Corp. (Nokia Corporation)
• Inventors: Lovell, Mark A., Sloan, Keith A.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US08/262,921
• Time in Patent Office: 686 Days
• Field of Search: 375/357, 375/356, 375/371, 375/375, 375/347, 375/226, 371/1, 371/29.1, 328/155, 328/63, 328/66, 328/67, 328/72, 328/137, 328/133, 327/2, 327/3, 327/20, 327/261, 327/262, 327/161, 327/147, 327/182, 327/183, 327/199, 327/202, 327/270, 327/276, 327/269, 327/298, 327/378, 327/392, 327/393, 327/144
• US Class Current: 375/371
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

In a telecommunication system having multiple timing subsystems receiving and distributing redundant timing signals, there is provided a circuitry for aligning first and second redundant timing signals and switching therebetween. The circuitry includes a selecting and switching circuitry for receiving the first and second redundant timing signals and designating one of the redundant timing signals as ACTIVE and the other as INACTIVE, and providing the ACTIVE timing signal as an output timing reference signal. The selecting and switching circuitry further switching the ACTIVE and INACTIVE timing signal designation and output timing reference signal in response to detecting fault or a clock switching command. The ACTIVE timing signal is provided to a first delay path having a programmable delay value, which delays it and produces a first output timing signal. A second delay path receives the INACTIVE redundant timing signal and produces a second output timing signal. The circuitry further includes a phase detector which receives the ACTIVE and INACTIVE output timing signals and generates a status signal indicative of phase relationship therebetween. The circuitry further provides for temperature compensation which measures and compensates for an effect of temperature change on the delay paths.

Claims

1. A circuitry for aligning first and second redundant timing signals and switching therebetween, comprising:

a selecting and switching circuitry for receiving said first and second redundant timing signals and designating one of said redundant timing signals as ACTIVE and the other as INACTIVE;

a first delay path having a programmable delay value coupled to said selecting circuitry, receiving said ACTIVE redundant timing signal and producing a first output timing signal;

a second delay path having a programmable delay value coupled to said selecting circuitry, receiving said INACTIVE redundant timing signal and producing a second output timing signal;

a phase detector coupled to said first and second delay paths, receiving said ACTIVE and INACTIVE output timing signals, and generating a status signal indicative of phase relationship therebetween; and

a controller coupled to said phase detector for controlling said programmable delay values of said first and second delay paths to phase align said ACTIVE and INACTIVE timing signals in response to said status signal.

2. The circuitry, as set forth in claim 1, wherein said selecting and switching circuitry switches said ACTIVE and INACTIVE timing signal designations in response to detecting fault in said ACTIVE timing signal.

3. The circuitry, as set forth in claim 1, wherein said selecting and switching circuitry switches said ACTIVE and INACTIVE timing signal designations in response to a clock switching command.

4. The circuitry, as set forth in claim 1, wherein said selecting circuitry selects said ACTIVE and INACTIVE timing signals by default.

5. The circuitry, as set forth in claim 1, wherein each of said first and second delay paths comprises:

a coarse delay circuitry having a plurality of delay elements of a coarse resolution; and

a fine delay circuitry coupled to said coarse delay circuitry and having a plurality of delay elements of a fine resolution.

6. The circuitry, as set forth in claim 1, wherein each of said first and second delay paths comprises:

a coarse delay circuitry having a plurality of delay elements of a coarse resolution;

a medium delay circuitry coupled to said coarse delay circuitry and having a plurality of delay elements of a medium resolution; and

a fine delay circuitry coupled to said medium delay circuitry and having a plurality of delay elements of a fine resolution.

7. The circuitry, as set forth in claim 1, wherein each of said first and second delay paths comprises:

a coarse delay stage being incrementally programmable at a coarse resolution;

a medium delay stage coupled to said coarse delay stage and being incrementally programmable at a medium resolution; and

a fine delay stage coupled to said medium delay stage and being incrementally programmable at a fine resolution.

8. The circuitry, as set forth in claim 1, further comprising a preferred tap register coupled to said first and second delay paths and storing a preferred delay value for delaying said ACTIVE timing signal.

9. The circuitry, as set forth in claim 8, further comprising a temperature compensation circuitry for changing said preferred delay value stored in said preferred tap register in response to changes in temperature.

10. The circuitry, as set forth in claim 1, further comprising a temperature compensation circuitry for adjusting said programmable delay value of said programmable delay paths in response to changes in temperature.

11. The circuitry, as set forth in claim 10, wherein said temperature compensation circuitry comprises:

a programmable temperature delay path receiving said ACTIVE timing signal and producing a delayed timing signal delayed by a programmable delay value;

a temperature phase detector coupled to said programmable temperature delay path, receiving said ACTIVE timing signal and said delayed timing signal, and generating a temperature phase lock signal indicative of phase lock therebetween; and

a control circuitry coupled to said temperature phase detector, controlling the delay of said programmable temperature delay path for periodically measuring a clock period of said ACTIVE timing signal, comparing said measured clock periods and computing a delay adjustment therefrom.

12. The circuitry, as set forth in claim 11, wherein said programmable temperature delay path includes first and second parallel delay path portions for differentially delaying said ACTIVE timing signal and producing first and second delayed ACTIVE timing signals, and said temperature phase detector receiving said first and second delayed ACTIVE timing signals and indicating phase alignment thereof.

13. The circuitry, as set forth in claim 1, wherein said second delay path delaying said INACTIVE redundant timing signal includes first and second parallel delay path portions designated as a master and slave path portions, receiving said INACTIVE timing signal and having programmable delay values, said controller further controls said programming delay values of said master and slave path portions to phase align said master path portion timing signal with said ACTIVE timing signal, and to further phase align said slave path portion timing signal with said master path portion timing signal.

14. The circuitry, as set forth in claim 13, wherein said controller switches said master and slave path portion designations in response to achieving phase lock therebetween and said master path portion reaching a maximum or minimum delay.

15. The circuitry, as set forth in claim 1, wherein said controller computes an average delay value and controlling said programmable delay value of said second delay path to align said INACTIVE timing signal with said ACTIVE timing signal.

16. The circuitry, as set forth in claim 1, wherein said phase detector comprises:

a phase processor receiving a first and second signals for alignment and generating a PHASE DIRECTION vector and a PHASE CLOCK;

a loss of clock circuitry coupled to said phase processor, receiving said PHASE CLOCK and generating a LOSS OF PHASE CLOCK signal; and

an output processor coupled to said phase processor and said loss of clock circuitry and generating delay path control signals in response to said PHASE DIRECTION vector and said LOSS OF PHASE CLOCK signals.

17. In a telecommunication system having multiple timing subsystems receiving and distributing redundant timing signals, there is provided a circuitry for aligning first and second redundant timing signals and switching therebetween, comprising:

a selecting and switching circuitry for receiving said first and second redundant timing signals and designating one of said redundant timing signals as ACTIVE and the other as INACTIVE, and providing said ACTIVE timing signal as an output timing reference signal, said selecting and switching circuitry further switching said ACTIVE and INACTIVE timing signal designation and said output timing reference signal in response to receiving a loss of frame loss of clock, or a clock switching signal;

a first delay path having a programmable delay value coupled to said selecting circuitry, receiving said ACTIVE redundant timing signal and producing a first output timing signal;

a second delay path having a programmable delay value coupled to said selecting circuitry, receiving said INACTIVE redundant timing signal and producing a second output timing signal;

a phase detector coupled to said first and second delay paths, receiving said ACTIVE and INACTIVE output timing signals, and generating a status signal indicative of phase relationship therebetween;

a temperature compensation circuit coupled to said first and second delay paths and measuring an effect of temperature change on said delay paths;

a controller coupled to said phase detector for controlling said programmable delay values of said first and second delay paths to phase align said output timing signals in response to said status signal, and further coupled to said temperature compensation circuit for adjusting said programmable delay values in response to said measured effect of temperature change on said delay paths.

18. The circuitry, as set forth in claim 17, wherein each of said first and second delay paths comprises:

a coarse delay circuitry having a plurality of delay elements of a coarse resolution;

a medium delay circuitry coupled to said coarse delay circuitry and having a plurality of delay elements of a medium resolution; and

a fine delay circuitry coupled to said medium delay circuitry and having a plurality of delay elements of a fine resolution.

19. The circuitry, as set forth in claim 17, wherein each of said first and second delay paths comprises:

a coarse delay stage being incrementally programmable at a coarse resolution;

a medium delay stage coupled to said coarse delay stage and being incrementally programmable at a medium resolution; and

a fine delay stage coupled to said medium delay stage and being incrementally programmable at a fine resolution.

20. The circuitry, as set forth in claim 17, further comprising a preferred tap register coupled to said first and second delay paths and storing a preferred delay value for delaying said ACTIVE timing signal.

21. The circuitry, as set forth in claim 20, further comprising a temperature compensation circuitry for changing said preferred delay value stored in said preferred tap register in response to changes in temperature.

22. The circuitry, as set forth in claim 17, further comprising a temperature compensation circuitry for adjusting said programmable delay value of said programmable delay paths in response to changes in temperature.

23. The circuitry, as set forth in claim 22, wherein said temperature compensation circuitry comprises:

a programmable temperature delay path receiving said ACTIVE timing signal and producing a delayed timing signal delayed by a programmable delay value;

a temperature phase detector coupled to said programmable temperature delay path, receiving said ACTIVE timing signal and said delayed timing signal, and generating a temperature phase lock signal indicative of phase lock therebetween; and

a control circuitry coupled to said temperature phase detector, controlling the delay of said programmable temperature delay path for periodically measuring a clock period of said ACTIVE timing signal, comparing said measured clock periods and computing a delay adjustment therefrom.

24. The circuitry, as set forth in claim 22, wherein said programmable temperature delay path includes first and second parallel delay path portions for differentially delaying said ACTIVE timing signal and producing first and second delayed ACTIVE timing signals, and said temperature phase detector receiving said first and second delayed ACTIVE timing signals and indicating phase alignment thereof.

25. The circuitry, as set forth in claim 17, wherein said first and second delay paths each includes first and second parallel delay path portions.

26. A method for aligning and switching between first and second redundant timing signals, comprising the steps of:

selecting one of said first and second timing signals as an ACTIVE timing signal and the other as an INACTIVE timing signal, and providing said ACTIVE timing signal as an output timing reference;

detecting a phase relationship of said ACTIVE and INACTIVE timing signals;

incrementally delaying said INACTIVE timing signal until said detected phase relationship of said INACTIVE timing signal and said ACTIVE timing signal is in phase alignment; and

switching said ACTIVE and INACTIVE timing signal designation and said output timing reference signal in response to receiving a loss of frame or loss of clock signal for said ACTIVE timing signal or a clock switching command.

27. The method, as set forth in claim 26, wherein said incrementally delaying step comprises the steps of:

providing said ACTIVE timing signal to a first delay path;

providing said INACTIVE timing signal to a second delay path;

controllably delaying said ACTIVE timing signal by a preferred delay amount; and

incrementally adjusting the delay of said second delay path until said INACTIVE timing signal is in phase alignment with said ACTIVE timing signal.

28. The method, as set forth in claim 27, wherein said incrementally adjusting step comprises the steps of:

locating respective edges in said ACTIVE and INACTIVE timing signals;

determining a leading or lagging phase relationship between said located edges; and

incrementing or decrementing the delay of said INACTIVE timing signal in response to said leading or lagging phase relationship, respectively.

29. The method, as set forth in claim 27, further comprising the steps of:

periodically detecting an effect of changing temperature on the delay of said ACTIVE timing signal;

adjusting said preferred delay amount in response to said detected effect of changing temperature.

30. The method, as set forth in claim 29, wherein said changing temperature effect detecting step comprises the steps of:

providing said ACTIVE timing signal to both said first and second delay paths;

noting and comparing the difference in the amount of delay in said first and second delay paths; and

incrementally delaying said ACTIVE timing signal on said second delay path until said ACTIVE timing signals on said first and second delay paths are in phase alignment.

31. The method, as set forth in claim 29, wherein said changing temperature effect detecting step comprises the steps of:

providing said ACTIVE timing signal to said first delay path and a temperature delay path;

noting and comparing the difference in the amount of delay therein; and

incrementally delaying said ACTIVE timing signal on said temperature delay path until said ACTIVE timing signals on said first delay path and temperature delay path are in phase alignment.

32. The method, as set forth in claim 30, further comprising the step of computing a delay adjustment to said delay paths in response to said delay amount comparison.

33. The method, as set forth in claim 31, further comprising the step of computing a delay adjustment to said delay paths in response to said delay amount comparison.

34. The method, as set forth in claim 26, further comprising the steps of:

designating said INACTIVE timing signal as a master timing signal and a slave signal;

adjustably delaying said master timing signal to achieve phase alignment with said ACTIVE timing signal; and

adjustably delaying said slave timing signal to achieve phase alignment with said master timing signal.

35. The method, as set forth in claim 34, further comprising a step of switching said master and slave designations in response to achieving phase lock therebetween and said master path portion reaching a maximum or minimum delay.

36. The method, as set forth in claim 26, further comprising the steps of:

after said incrementally delaying step, storing a first delay value;

continuing incrementally delaying said INACTIVE timing signal until said INACTIVE timing signal is out of phase alignment with said ACTIVE timing signal and storing a second delay value; and

computing an average of said first and second delay values and delaying said INACTIVE timing signal by said computed average amount.

37. An integrated circuit for aligning and switching a first and second redundant timing reference signals, comprising:

circuitry for selecting from said first and second redundant timing reference signals an active timing reference;

a first delay pipeline receiving said first redundant timing reference signal, delaying said first redundant timing signal by a first programmable delay amount, and generating a first internal reference timing signal;

a second delay pipeline receiving said second redundant timing reference signal, delaying said second redundant timing signal by a second programmable delay amount, and generating a second internal reference timing signal;

a first phase detector coupled to said first delay pipeline and generating a first set of delay pipeline control signals in response to a phase relationship between said active timing reference and said first internal reference timing signal if said second redundant timing reference is designated as said active timing reference, and said first delay pipeline delaying said first redundant timing reference in response to said delay pipeline control signals;

a second phase detector coupled to said second delay pipeline and generating a second set of delay pipeline control signals in response to a phase relationship between said active timing reference and said second internal reference timing signal if said first redundant timing reference is designated as said active timing reference, and said second delay pipeline delaying said second redundant timing reference in response to said delay pipeline control signals; and

circuitry for switching said active timing reference between said first and second redundant timing reference signals in response to receiving a clock switching command or a loss of frame or loss of clock signal.

38. The integrated circuit, as set forth in claim 37, further comprising a PTV compensation circuit.

39. The integrated circuit, as set forth in claim 38, wherein said PTV compensation circuit comprises a third phase detector coupled to said first and second delay pipelines, detecting a phase relationship between said active timing reference and first or second internal reference timing signal, and generating a set of compensation delay pipeline control signals in response thereto.

40. The integrated circuit, as set forth in claim 37, wherein said first and second phase detectors each comprises:

a phase processor receiving said first or second internal reference timing signal, respectively, and said active timing reference, and generating a phase relationship therebetween and a phase clock indicative of a time lag between said internal reference timing signal and said active timing reference;

a loss of clock detector receiving said phase clock and said active timing reference and generating a loss signal in response to an absence of said phase clock; and

an output processor coupled to said phase processor and loss of clock detector, and generating said pipeline control signals in response to said phase direction, active timing reference, and said loss signal.