Open high speed bus for microcomputer system

• US 5,517,626 A
• Filed: 01/29/1993
• Issued: 05/14/1996
• Est. Priority Date: 05/07/1990
• Status: Expired due to Term

• Current Assignee: S3 Graphics Co., Ltd. (HTC Corporation)
• Original Assignee: S3 Inc. (SONICblue Incorporated)
• Inventors: Scott, David J., Sharma, Sanjay, Peng, Leon, Deora, Ajit J., Schopmeyer, Robert C., Archer, Jordan J., Stevens, Virgil, Leung, Kent S.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/011,449
• Time in Patent Office: 1,201 Days
• Field of Search: 395/325, 395/725, 395/425, 395/275, 395/290, 395/306, 395/457, 395/445, 395/853, 395/733, 395/735
• US Class Current: 710/110
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4217 with synchronous protocol

Abstract

An open high-speed local system bus for a microcomputer system which is decoupled from I/O and provides a consistent interface to the CPU subsystem, memory subsystem, graphics subsystem and peripheral subsystem. The local system bus supports discrete and burst transactions, pipelining in both the transactions, multiple microprocessor and distributed interrupts.

Claims

1. A local system bus for a micro-processor based computer system including a plurality of controllers connected between the local system bus and at least one micro-processor, a system memory or an I/O bus, one of the controllers being a bus master and another being a bus slave during a bus transaction, the local system bus comprising:

lines for carrying an address driven by the bus master and received by the bus slave;

lines for carrying data driven by the bus master and received by the bus slave during a write transaction or driven by the bus slave and received by the bus master during a read transaction;

lines for carrying signals generated by the bus master and received by the bus slave, for defining a transaction in progress;

lines for carrying control signals for micro-processor operations;

lines for carrying status signals asserted by the bus slave for indicating a status of the bus slave further comprising lines for carrying interrupt signals; and

lines for carrying arbitration signals, wherein the lines for carrying arbitration signals comprise a line for carrying a bus hold request for permitting another controller to gain control of the local system bus.

2. A local system bus as in claim 1, further comprising at least one line for carrying a signal for partial read and write operations.

3. A local system bus as in claim 1, further comprising at least one line for carrying a signal indicating a parity of the data.

4. A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line for carrying a signal indicating whether the transaction involves memory operations or I/O operations.

5. A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line for carrying a signal indicating data transactions or instruction fetch transactions.

6. A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line for carrying a signal indicating whether the transaction involves write operations or read operations.

7. A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line for carrying a signal indicating whether the transaction is a normal transaction or a locked transaction.

8. A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line for carrying a signal supporting copy-back operations.

9. A local system bus as in claim 1, wherein the lines for defining a transaction comprise a line carrying a signal for write-through cache operations.

10. A local system bus as in claim 1, wherein the control signal lines comprise a line carrying a signal indicating a valid address being on the local system bus.

11. A local system bus as in claim 1, wherein the control signal lines comprise a line for carrying a signal indicating an end of a data cycle.

12. A local system bus as in claim 1, wherein the control signal lines comprise a line for carrying a signal indicating a bit size of a bus master involved in a current cycle.

13. A local system bus as in claim 1, wherein the control signal lines comprise a line for carrying a signal indicating a bit size of a bus slave recipient of a current cycle.

14. A local system bus as in claim 1, wherein the control signal lines comprise a line for carrying a signal indicating a bus slave being ready to receive a next line address.

15. A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating the bus slave having provided valid data in response to a read or having accepted data in response to a write.

16. A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating the bus slave being not ready to handle a required transaction.

17. A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal asserted by a bus slave for extending a snoop cycle of a current transaction.

18. A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating a parity error on the lines for carrying data during a data cycle.

19. A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating that a non-master cache controller will retain a copy of addressed data in a current transaction.

20. A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating whether a current transaction is cacheable.

21. A local system bus as in claim 1, wherein the lines for carrying status signals comprise a line for carrying a signal indicating a processor controller intervening in the local system bus transaction.

22. A local system bus as in claim 1, further comprising lines for carrying interrupt signals.

23. A local system bus as in claim 22, wherein the lines for carrying interrupt signals comprise a line for carrying an interrupt request signal.

24. A local system bus as in claim 22, wherein the lines for carrying interrupt signals comprise a line for carrying a non-maskable interrupt signal.

25. A local system bus as in claim 22, further comprising an additional line for carrying a signal for resetting the micro-processor based computer system.

26. A local system bus as in claim 25, further comprising an additional line for carrying a local processor reset signal.

27. A local system bus as in claim 1, wherein the lines for carrying arbitration signals comprise a line for carrying a local system bus request signal.

28. A local system bus as in claim 1, wherein the lines for carrying arbitration signals comprise a line for carrying a local system bus grant signal to one of the controllers.

29. A local system bus as in claim 1, wherein the lines for carrying arbitration signals comprise a line for carrying an acknowledge signal indicating whether the local system bus is given up in response to a bus hold request.

30. A local system bus as in claim 1, further comprising lines for carrying signals supporting a distributed arbitration.

31. A local system bus as in claim 1, wherein each local system bus transaction comprises a sequence of phases.

32. A local system bus as in claim 31, wherein said phases comprise arbitration, command, address, data and status phases.

33. A local system bus as in claim 32, wherein the arbitration, command and address phases for a next transaction can start during the data phase of a present transaction.

34. A local system bus as in claim 33, wherein the local system bus operates at two bus speeds.

35. A local system bus as in claim 1, wherein the micro-processor based computer system comprises a peripheral control bus connected to the I/O bus and to each controller for programming peripheral devices connected to the local system bus.

36. A local system bus as in claim 35, wherein distributed interrupts are supported as follows:

an interrupt request being generated onto the local system bus by an interrupt controller;

an interrupt acknowledge sequence being generated by one of the controllers connected between the local system bus and the micro-processor and an interrupt vector being driven during the interrupt acknowledge;

the interrupt vector being captured by every controller connected between the local system bus and the micro-processor;

an interrupt signal generated by one of the controllers that is enabled by the captured interrupt vector being sent to an associated micro-processor, and a protection signal being generated by the enabled controller for preventing any of the controllers from acknowledging any subsequent interrupt request;

an interrupt acknowledger being generated by the associated micro-processor to the enabled controller; and

a prevention signal being released by the enabled controller in response to receiving of the interrupt knowledge.

37. A local system bus as in claim 36, wherein the interrupt vector is carried on the peripheral control bus to enable any of the controllers to capture the interrupt vector.

38. A local system bus as in claim 1, wherein an arbitration for control of the local system bus is as follows:

signals being generated onto the local system bus by a cache controller that requires the local system bus;

a selected bus owner being determined in response to the generated signals;

the selected bus owner waiting for a current bus owner to relinquish the local system bus by driving a grant signal onto the local system bus; and

the selected bus owner assuming control of the local system bus.

39. A micro-processor based computer system including at least a first micro-processor and a cache memory, a system memory, and input/output devices, the computer system comprising:

a local system bus for connecting the micro-processor to the cache memory;

an input/output bus for connecting to the input/output devices;

a first controller for connecting the local system bus to the I/O bus;

wherein the local system bus operates at a higher data rate than does the input/output bus;

at least one cache controller connected between the first micro-processor and the local system bus; and

a second cache controller connected between the local system bus and the system memory.

40. A computer system as in claim 39, wherein the input/output bus is one of an ISA, MCA or EISA bus.

41. A computer system as in claim 39, further comprising a peripheral control connected to the input/output bus and at least one cache controller for programming peripheral devices connected to the local system bus.

42. The computer system of claim 41, further comprising means for allowing a peripheral device connected to the local system bus to control a speed of data transfers to or from another peripheral device connected to the local system bus.

43. A computer system as in claim 39, wherein the first micro-processor has a first clocking scheme, and further comprising a second micro-processor having a second clocking scheme differing from the first clocking scheme and connected to the local system bus.

44. The computer system of claim 39, further comprising means for connecting at least a second micro-processor to the local system bus.