Nonvolatile memory card with an address table and an address translation logic for mapping out defective blocks within the memory card

• US 5,524,231 A
• Filed: 06/30/1993
• Issued: 06/04/1996
• Est. Priority Date: 06/30/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Brown, David M.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Thai, Tuan V.
• Application Number:
  US08/086,043
• Time in Patent Office: 1,070 Days
• Field of Search: 364/200, 395/400, 395/425, 395/428, 395/421.01, 365/52, 365/185.09, 365/185.29, 365/195, 365/196, 365/900, 235/380
• US Class Current: 711/101
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A nonvolatile memory card includes first memory and a second memory. The first memory includes a first block and a second block, each can be addressed by a first block address and a second block address, respectively. The second memory includes a third block and a fourth block, each can be addressed by a third block address and a fourth block address, respectively. An address table is used for storing (1) each of the first, second, third, and fourth block addresses and (2) a first, a second, a third, and a fourth status data, each indicating the operational condition of one of the first, second, third, and fourth blocks, respectively. Each of the first, second, third, and fourth status data can be in a first state and a second state. When a particular one of the first, second, third, and fourth blocks is non-operational, the corresponding one of the first, second, third, and fourth status data is at the first state. An address translation logic is coupled to (1) the address table and (2) the first and second memories for receiving external addresses to access memory locations within the first and second memories, and for converting the external addresses to access the memory locations in only the operational ones of the first, second, third, and fourth blocks such that the external addresses are consecutive while at least one of the first, second, third, and fourth blocks can be non-operational. Each of the external addresses includes a block address and an address associated with the block address.

Claims

1. A nonvolatile memory card, comprising:

(A) a first memory and a second memory, wherein the first memory includes a first block and a second block, each being addressed by a first block address and a second block address, respectively, wherein the second memory includes a third block and a fourth block, each being addressed by a third block address and a fourth block address, respectively;

(B) an address table stored in an electrically erasable and programmable read-only memory separate from the first and second memories for storing (1) each of the first, second, third, and fourth block addresses and (2) a first, a second, a third, and a fourth status data, each indicating an operational condition of one of the first, second, third, and fourth blocks, respectively, wherein each of the first, second, third, and fourth status data can be in a first state and a second state, wherein when a particular one of the first, second, third, and fourth blocks is non-operational, the corresponding one of the first, second, third, and fourth status data is at the first state;

(C) a set of program instructions for translating external addresses received from an external circuitry into memory addresses that access memory locations in only the operational ones of the first, second, third, and fourth blocks in accordance with the status data of the first, second, third, and fourth block stored in the address table such that the external addresses are consecutive while at least one of the first, second, third, and fourth blocks can be non-operational, wherein each of the external addresses includes a block address and an address associated with the block address.

2. The memory card of claim 1, further comprising a capacity indication logic coupled to the address table for calculating a total number of operational blocks among the first, second, third, and fourth blocks and for indicating to the external circuitry the total number of operational blocks of the memory card.

3. The memory card of claim 2, wherein the external addresses include a number of external block addresses corresponding only to a total number of operational blocks of the first and second memories, wherein the external block addresses are consecutive.

4. The memory card of claim 3, wherein when the external circuitry applies an external address to the memory card that includes a first external block address and when the first block is non-operational and the second block is operational, the address translation logic converts the first external block address of the external address into the second block address, wherein when the external circuitry applies an external address to the memory card that includes a second external block address and when the first block is non-operational and the second and third blocks are operational, the address translation logic converts the second external block address of the external address into the third block address.

5. The memory card of claim 1, wherein the first memory includes a first plurality of blocks, including the first and second blocks, wherein the second memory includes a second plurality of blocks, including the third and fourth blocks, wherein each of the first and second plurality of blocks includes a plurality of memory locations.

6. The memory card of claim 5, wherein the address table stores block addresses of each of the first and second plurality of blocks and the status data of an operational condition of each of the first and second plurality of blocks, respectively.

7. The memory card of claim 1, wherein each of the first and second memories is an electrically programmable and electrically erasable read-only memory.

8. A nonvolatile memory card, comprising:

(A) a first memory and a second memory, wherein the first memory includes a first block and a second block, each being addressed by a first block address and a second block address, respectively, wherein the second memory includes a third block and a fourth block, each being addressed by a third block address and a fourth block address, respectively;

(B) an address table stored in an electrically erasable and programmable read-only memory separate from the first and second memories for storing (1) each of the first, second, third, and fourth block addresses and (2) a first, a second, a third, and a fourth status data, each indicating an operational condition of one of the first, second, third, and the fourth blocks, respectively, wherein each of the first, second, third, fourth status data can be in a first state and a second state, wherein when a particular one of the first, second, third, and fourth blocks is non-operational, the corresponding one of the first, second, third, and fourth status data is at the first state;

(C) a set of program instructions for translating external address received for external circuitry to memory addresses that access memory locations in only the operational ones of the first, second, third, and fourth blocks in accordance with the status data of the first, second, third, and fourth blocks stored in the address table such that the external addresses are consecutive while at least one of the first, second, third, and fourth blocks can be non-operational, wherein each of the external addresses includes a block address and an address associated with the block address; and

(D) a capacity indication logic coupled to the address table for calculating a total number of operational blocks of the first, second, third, and fourth blocks and for indicating to the external circuitry the total number of operational blocks of the memory card.

9. The memory card of claim 8, wherein the external addresses include a number of external block addresses corresponding only to a total number of operational blocks of the first and second memories, wherein the external block addresses are consecutive.

10. The memory card of claim 9, wherein when the external circuitry applies an external address to the memory card that includes a first external block address and when the first block is non-operational and the second block is operational, the address translation logic converts the first external block address of the external address into the second block address, wherein when the external circuitry applies an external address to the memory card that includes a second external block address and when the first block is non-operational and the second and third blocks are operational, the address translation logic converts the second external block address of the external address into the third block address.

11. The memory card of claim 8, wherein the first memory includes a first plurality of blocks, including the first and second blocks, wherein the second memory includes a second plurality of blocks, including the third and fourth blocks, wherein each of the first and second plurality of blocks includes a plurality of memory locations.

12. The memory card of claim 11, wherein the address table stores block addresses of each of the first and second plurality of blocks and the status data of an operational condition of each of the first and second plurality of blocks, respectively.

13. The memory card of claim 8, wherein each of the first and second memories is an electrically programmable and electrically erasable read-only memory.