Computer system having an improved memory architecture

• US 5,526,506 A
• Filed: 09/04/1990
• Issued: 06/11/1996
• Est. Priority Date: 12/28/1970
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US07/578,041
• Time in Patent Office: 2,107 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/400, 395/425, 395/550, 395/600, 395/800, 395/700, 365/191, 365/194, 365/205, 365/222, 365/189.05, 365/189.01
• US Class Current: 711/111
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/23094 Debounce key
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 : Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35381 : Convert in real time input peripheral data to processor data, ouput data format
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/35588 : Pack, compress data efficiently in memory
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36227 : Assist operator to calculate unknown points, contours
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36395 : Load local computer program from host, data transfer ram to rom, BTR
• CPC Class Codes: G05B 2219/36502 : Ram for variable servo data, rom for fixed servo routine
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36506 : Store in Rom and Ram
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 12/0215 : with look ahead addressing means
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 3/0383 : Signal control means within the pointing device
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G09G 5/18 : Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: G09G 5/20 : Function-generator circuits, e.g. circle generators line or curve smoothing circuits
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 13/0033 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/04 : using optical elements ; using other beam accessed elements, e.g. electron or ion beam
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H03H 17/0291 : Digital and sampled data filters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Memory technologies for storing filter samples include RAMs and CCDs. Adaptive memory capability and memory servo capability improve memory characteristics. In a RAM embodiment, a detector is used to detect a memory address condition and to control the memory and the memory address register in response thereto. In a CCD embodiment, a detector is used to detect a memory reference signal and to refresh the memory signals in response thereto. Improved memory refresh, memory performance, and memory capacity enhance system characteristics. Improved memory architecture provides advantages of increased speed, lower cost, and efficiency of implementation. Information stored in memory can be scanned out at a rate greater than the addressing rate associated with the memories. This permits higher speed operation with lower cost memories. Use of an output buffer, such as a FIFO, permits normalization of memory clock rates.

Claims

1. A memory system comprising:

a plurality of memories storing data;

an address generator generating addresses;

an accessing circuit coupled to the memories and to the address generator and accessing data stored by the memories in response to an address generated by the address generator;

a processor coupled to the accessing circuit and processing data accessed by the accessing circuit;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the addresses generated by the address generator, wherein at least one of the detector circuits is a change detector circuit generating a change detector signal in response to detection of a change in an address generated by the address generator relative to a previously generated address; and

a delay circuit coupled to receive at least one change detector signal from the detector circuits and coupled to delay generating of an address by the address generator in response to receipt of the change detector signal.

2. A memory system as set forth in claim 1, wherein the memories include at least one dynamic random access memory storing data in dynamic form and wherein the system further comprises a refresh circuit refreshing the data stored by the dynamic random access memory in response to the processing of data by the processor.

3. A memory system as set forth in claim 1, wherein each address generated by the address generator has a less significant bit portion and has a more significant bit portion and wherein the change detector circuit includes an overflow circuit generating the change detector signal in response to detection of an overflow from the less significant bit portion to the more significant bit portion when an address is generated by the address generator.

4. A memory system as set forth in claim 1, wherein each address generated by the address generator has less significant bits and more significant bits and wherein the change detector circuit includes a buffer circuit coupled to the address generator and storing the more significant bits of a previously generated address and a comparator circuit coupled to the buffer circuit and to the address generator and generating the change detector signal in response to detection of a change in the more significant bits of an address generated by the address generator relative to the more significant bits of the previously generated address stored by the buffer circuit.

5. A memory system as set forth in claim 1, wherein each address generated by the address generator has a less significant portion and a more significant portion and wherein the change detector circuit includes an anticipatory circuit generating the change detector signal in response to anticipation of a change in the more significant portion of an address generated by the address generator relative to a more significant portion of a previously generated address.

6. A memory system as set forth in claim 1, further comprising a mode circuit generating a mode signal identifying one of a plurality of modes, wherein the plurality of detector circuits include a modal detector circuit generating a modal detector signal in response to the mode signal.

7. A memory system as set forth in claim 1, wherein the delaying circuit includes a flip-flop circuit delaying generating of an address by the address generator in response to at least one of the detector signals and wherein the address generator generates the addresses sequentially in time.

8. A memory system as set forth in claim 1, wherein at least one of the memories includes:

a refreshable memory circuit storing data in response to a refresh signal;

a control circuit generating a control signal in response to the accessing of data stored by the refreshable memory circuit by the accessing circuit to resolve contention between accessing of data stored by the refreshable memory circuit by the accessing circuit and refreshing of the refreshable memory circuit by a refresh circuit; and

a refresh circuit coupled to receive the control signal from the control circuit and coupled to generate the refresh signal in response to the received control signal.

9. A memory system as set forth in claim 1, wherein at least one of the memories includes:

a refreshable memory circuit storing data;

a control circuit generating a refresh control signal in response to the processing of data by the processor to resolve contention between the processing of data by the processor and refreshing of the refreshable memory circuit by a refresh circuit; and

a refresh circuit coupled to receive the refresh control signal from the control circuit and to refresh the refreshable memory circuit to preserve data stored therein in response to the refresh control signal.

10. A memory system as set forth in claim 1, wherein the memories include at least one dynamic ranmdom access memory storing data.

11. A memory system as set forth in claim 1, further comprising a program memory storing a computer program;

wherein the processor includes a stored program computer coupled to the program memory and processing data accessed by the accessing circuit in response to the program.

12. A memory system as set forth in claim 1, wherein the processor includes a display processor coupled to the accessing circuit and processing data accessed by the accessing circuit to generate display data;

wherein the system further comprises a display monitor coupled to the display processor and displaying an image in response to the display data.

13. A memory system as set forth in claim 1, wherein the processor includes an artificial intelligence processor processing data accessed by the accessing circuit to generate artificial intelligence data.

14. A memory system as set forth in claim 1, wherein the processor includes an image processor processing data accessed by the accessing circuit to generate image display data;

wherein the system further comprises a display monitor coupled to the image processor and displaying an image in response to the image display data.

15. A memory system as set forth in claim 1, wherein the processor includes a television image processor processing data accessed by the accessing circuit to generate television image data;

wherein the system further comprises a television monitor coupled to the television image processor and displaying a television image in response to the television image data.

16. A memory system as set forth in claim 1, further comprising a read only memory storing a computer program;

wherein the processor includes a stored program computer coupled to the read only memory and processing data accessed by the accessing circuit in response to the program stored by the read only memory.

17. A memory system as set forth in claim 1, wherein the plurality of memories include a dynamic cache memory dynamically storing data, the cache memory being coupled to communicate data between the cache memory and the processor and to communicate data between the cache memory and at least one other of the plurality of memories.

18. A memory system as set forth in claim 1, wherein the memories include at least one random access memory storing data and wherein the system further comprises:

a scanout address update circuit coupled to at least one of the plurality of detector circuits and updating the addresses generated by the address generator at a first address update rate in response to a first state of a selected detector signal; and

a re-addressing address update circuit coupled to at least one of the plurality of detector circuits and updating the addresses generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the selected detector signal.

19. A memory system as set forth in claim 1, wherein the memories include at least one random access memory storing data and wherein the system further comprises:

an external scanout address update circuit coupled to at least one of the detector circuits and updating the addresses generated by the address generator at a first address update rate in response to a first state of a selected detector signal; and

a re-addressing address update circuit coupled to at least one of the plurality of detector circuits and updating the addresses generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the selected detector signal different from the first state.

20. A memory system comprising:

a plurality of memories storing data;

an address generator generating addresses;

a processor coupled to receive data from the memories at addresses therein indicated by the addresses generated by the address generator and to process the received data;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the addresses generated by the address generator, the plurality of detector circuits including at least one change detector circuit generating a change detector signal in response to detection of a change in an address generated by the address generator; and

a delaying circuit coupled to receive at least one detector signal from the plurality of detector circuits and to delay generating of an address by the address generator in response to the received change detector signal.

21. A memory system as set forth in claim 20, wherein the memories include a dynamic random access memory storing data and wherein the system further comprises a refresh circuit coupled to the processor and to the dynamic random access memory and refreshing data stored by the dynamic random access memory in response to the processing of the data by the processor.

22. A memory system as set forth in claim 20, wherein the change detector circuit includes an overflow circuit coupled to the address generator and generating the change detector signal in response to detection of an overflow related to generating of an address by the address generator and wherein the address generator generates the addresses in time sequence one after another.

23. A memory system as set forth in claim 20, wherein the addresses generated by the address generator have less significant bits and more significant bits, wherein the change detector circuit includes a buffer circuit coupled to the address generator and storing the more significant bits of a previously generated address and a comparator circuit coupled to the buffer circuit and to the address generator and generating the change detector signal in response to detection of a change in the more significant bits of an address generated by the address generator relative to an address previously generated by the address generator.

24. A memory system as set forth in claim 20, wherein the change detector circuit includes an anticipatory circuit coupled to the address generator and generating a change detector signal in response to anticipation of a change in the address generated by the address generator.

25. A memory system as set forth in claim 20, further comprising a mode circuit generating a mode signal identifying a plurality of modes, wherein the plurality of detector circuits include a modal detector circuit generating a detector signal in response to the mode signal.

26. A memory system as set forth in claim 20, wherein the delaying circuit includes a flip-flop circuit coupled to at least one of the detector circuits and delaying generating of an address by the address generator in response to at least one of the detector signals.

27. A memory system as set forth in claim 20, wherein at least one of the memories includes:

a refreshable memory circuit storing data;

a control circuit coupled to the processor and to the refreshable memory and generating a refresh control signal in response to the processing of data stored by the memory by the processor to resolve contention between the processing of data by the processor and refreshing of the refreshable memory circuit by a refresh circuit; and

a refresh circuit coupled to the refreshable memory and to the control circuit and refreshing the refreshable memory to preserve the data stored therein in response to the refresh control signal.

28. A memory system as set forth in claim 20, wherein at least one of the memories includes:

a dynamic random access memory circuit storing data;

a control circuit coupled to the processor and generating a refresh control signal in response to the processing of data by the processor to resolve contention between the processing of data by the processor and refreshing of the refreshable dynamic random access memory by a refresh circuit; and

a refresh circuit coupled to the dynamic random access memory and to the control circuit and refreshing the dynamic random access memory circuit to preserve the data stored therein in response to the refresh control signal.

29. A memory system as set forth in claim 20, wherein the memories include at least one dynamic random access memory storing data.

30. A memory system as set forth in claim 20, further comprising a program memory storing a computer program;

wherein the processor includes a stored program computer coupled to the program memory and processing data stored by the memories in response to the program stored by the program memory.

31. A memory system as set forth in claim 20, wherein the processor includes a display processor processing data stored by the memories to generate display data;

wherein the system further comprises a display monitor coupled to the display processor and displaying an image in response to the display data.

32. A memory system as set forth in claim 20, wherein the processor includes an artificial intelligence processor processing data stored by the memories to generate artificial intelligence data.

33. A memory system as set forth in claim 20, wherein the processor includes an image processor processing data stored by the memories to generate image display data;

the system further comprising a display monitor coupled to the image processor and displaying an image in response to the image display data.

34. A memory system as set forth in claim 20, wherein the processor includes a television image processor processing data stored by the memories to generate television image data;

wherein the system further comprises a television monitor coupled to the television image processor and displaying a television image in response to the television image data.

35. A memory system as set forth in claim 20, further comprising a read only memory storing a computer program;

wherein the processor includes a stored program computer coupled to the read only memory and processing data stored by the memory in response to the program stored by the read only memory.

36. A memory system as set forth in claim 20, wherein the memories include a cache memory storing data.

37. A memory system as set forth in claim 20, wherein at least one of the memories includes a random access memory storing data and wherein the system further comprises:

a scanout address update circuit coupled to at least one of the plurality of detector circuits and updating the addresses generated by the address generator at a first address update rate in response to a first state of a selected detector signal; and

a re-addressing address update circuit coupled to at least one of the plurality of detector circuits and updating the addresses generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the selected detector signal.

38. A memory system as set forth in claim 20, wherein at least one of the memories includes a random access memory storing data and wherein the system further comprises:

an external scanout address update circuit coupled to at least one of the plurality of detector circuits and updating the addresses generated by the address generator at a first address update rate in response to a first state of a selected detector signal; and

a re-addressing address update circuit coupled to at least one of the detector circuits and updating the addresses generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the selected detector signal.

39. A memory system comprising:

a plurality of memories storing data to be processed;

an address generator generating addresses;

a processor coupled to the memories and coupled to the address generator, the processor processing data stored by the memories in response to the addresses generated by the address generator; and

a plurality of detector circuits coupled to receive the addresses generated by the address generator and generating a plurality of detector signals in response to the received addresses.

40. A memory system as set forth in claim 39, wherein at least one of the memories includes a dynamic random access memory dynamically storing data and wherein the system further comprises a refresh circuit coupled to the memories and to the processor and refreshing data stored by the dynamic random access memory in response to the processing of the data by the processor.

41. A memory system as set forth in claim 39, wherein at least one of the plurality of detector circuits includes an overflow circuit generating a detector signal in response to detection of an overflow related to generation of an address by the address generator.

42. A memory system as set forth in claim 39, wherein the addresses generated by the address generator have a plurality of less significant bits and have a plurality of more significant bits and wherein at least one of the plurality of detector circuits includes a buffer circuit coupled to the address generator and storing the plurality of more significant bits of each address and a comparator circuit coupled to the address generator and and to the buffer circuit and generating a change detector signal in response to detection of a change in the plurality of more significant bits of an address generated by the address generator relative to the plurality of more significant bits of a previously generated address stored by the buffer circuit.

43. A memory system as set forth in claim 39, wherein at least one of the plurality of detector circuits includes an anticipatory circuit generating a change detector signal in response to anticipation of a change in an address generated by the address generator.

44. A memory system as set forth in claim 39, further comprising a mode circuit generating a mode signal identifying a plurality of modes and a modal detector circuit generating a detector signal in response to the mode signal.

45. A memory system as set forth in claim 39, wherein at least one of the memories includes:

a refreshable memory circuit storing data in response to a refresh signal;

a control circuit generating a refresh control signal in response to the processing of data stored by the memories by the processor to resolve contention between the processing of the data by the processor and refreshing of the refreshable memory circuit by a refresh circuit; and

a refresh circuit coupled to the control circuit and refreshing the refreshable memory to preserve data stored therein in response to the refresh control signal.

46. A memory system as set forth in claim 39, wherein at least one of the memories includes:

a dynamic random access memory circuit storing data in response to a refresh signal;

a control circuit generating a refresh control signal in response to the processing of data by the processor to resolve contention between the processing of data by the processor and refreshing of the dynamic random access memory circuit by a refresh circuit; and

the refresh circuit coupled to the control circuit and refreshing the dynamic random access memory circuit to preserve data stored therein in response to the refresh control signal.

47. A memory system as set forth in claim 39, wherein at least one of the memories includes a dynamic random access memory storing data.

48. A memory system as set forth in claim 39, further comprising a program memory storing a computer program;

wherein the processor includes a stored program computer coupled to the program memory and processing the data stored by the memories in response to the program stored by the program memory.

49. A memory system as set forth in claim 39, wherein the processor includes a display processor processing the data stored by the memories to generate display data;

wherein the system further comprises a display monitor coupled to the display processor and displaying an image in response to the display data.

50. A memory system as set forth in claim 39, wherein the processor includes an artificial intelligence processor processing the data stored by the memories to generate artificial intelligence data.

51. A memory system as set forth in claim 39, wherein the processor includes an image processor processing the data stored by the memories to generate image display data;

the system further comprising a display monitor coupled to the image processor and displaying an image in response to the image display data.

52. A memory system as set forth in claim 39, wherein the processor includes a television image processor processing the data stored by the memories to generate television image data;

wherein the system further comprises a television monitor coupled to the television image processor and displaying a television image in response to the television image data.

53. A memory system as set forth in claim 39, further comprising a read only memory storing a computer program;

wherein the processor includes a stored program computer coupled to the read only memory and processing the data stored by the memories in response to the program stored by the read only memory.

54. A memory system as set forth in claim 39, wherein the memories include a cache memory storing data.

55. A memory system as set forth in claim 39, wherein at least one of the memories includes a random access memory storing data and wherein the system further comprises:

a scanout address update circuit coupled to the plurality of detector circuits and updating each address generated by the address generator at a first address update rate in response to a first state of a selected detector signal; and

a re-addressing address update circuit coupled to the plurality of detector circuits and updating each address generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the selected detector signal.

56. A memory system as set forth in claim 39, wherein at least one of the memories includes a random access memory storing data and wherein the system further comprises:

an external scanout address update circuit coupled to the plurality of detector circuits and updating each address generated by the address generator at a first address update rate in response to a first state of a selected detector signal; and

a re-addressing address update circuit coupled to the plurality of detector circuits and updating each address generated by the address generator at a second address update rate that is lower than the first address update rate in response to a second state of the selected detector signal.

57. A memory system comprising:

a plurality of memories storing data;

an address generator generating an address;

an accessing circuit coupled to receive an address generated by the address generator, coupled to the plurality of memories and coupled to access data stored by at least one of the memories at the received address in response to the received address;

a processor coupled to the accessing circuit and processing data accessed by the accessing circuit; and

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address.

58. A memory system as set forth in claim 57, further comprising:

a mode circuit generating a mode signal identifying a plurality of modes;

wherein the plurality of detector circuits includes a modal detector circuit coupled to receive the mode signal and generate a detector signal in response to the received mode signal; and

further comprising

a delaying circuit coupled to receive the modal detector signal from the modal detector circuit and delay generation of an address by the address generator in response to the received detector signal.

59. A memory system comprising:

a plurality of memories storing data, at least one of the memories being a dynamic random access memory storing data in dynamic form;

an address generator generating an address;

an accessing circuit coupled to receive the address generated by the address generator, coupled to the plurality of memories and coupled to access data stored by one of the memories at the received address;

a processor coupled to the accessing circuit and processing data accessed by the accessing circuit;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address; and

a refresh circuit coupled to the dynamic random access memory and to the processor and refreshing data stored by the dynamic random access memory in response to the processing of data by the processor.

60. A memory system comprising:

a plurality of memories storing data;

an address generator generating addresses;

an accessing circuit coupled to receive the addresses generated by the address generator, coupled to the plurality of memories and coupled to access data stored by the memories in response to the received addresses;

a processor coupled to the accessing circuit and processing the accessed data; and

an overflow detector circuit coupled to the address generator and generating a detector signal in response to detection of an overflow related to generation of an address by the address generator.

61. A memory system comprising:

a plurality of memories storing data;

an address generator generating addresses having more significant bits and less significant bits;

an accessing circuit coupled to receive addresses generated by the address generator and to access data stored by the memories in response to the received address;

a processor coupled to the accessing circuit and processing the accessed data;

a buffer circuit coupled to the address generator and storing the more significant bits of a generated address; and

a comparator detector circuit coupled to the address generator and to the buffer circuit and generating a detector signal in response to detection of a change in the more significant bits of an address generated by the address generator relative to the more significant bits stored by the buffer circuit.

62. A memory system comprising:

a plurality of memories storing data;

an address generator generating a plurality of addresses;

an accessing circuit coupled to receive generated addresses from the address generator, coupled to the plurality of memories and coupled to access data stored by the plurality of memories in response to the received addresses;

a processor coupled to the accessing circuit and processing the accessed data; and

an anticipatory detector circuit coupled to generate a detector signal in response to anticipation of a change in an address generated by the address generator.

63. A memory system comprising:

a plurality of memories storing data;

an address generator generating addresses;

an accessing circuit coupled to receive an address from the address generator and coupled to access data stored by the plurality of memories in response to the received address;

a processor coupled to the accessing circuit and processing the accessed data;

a plurality of change detectors coupled to the address generator and generating a plurality of change detector signals in response to detection of changes in the address generated by the address generator; and

a plurality of delaying circuits coupled to the plurality of change detector circuits and to the address generator and delaying generating of an address by the address generator in response to the change detector signals.

64. A memory system comprising:

a refreshable memory circuit storing data;

a control circuit generating a refresh control signal in response to processing by a processor of data stored by the memory to resolve contention between the processing of data by the processor and refreshing of the refreshable memory circuit by a refresh circuit;

the refresh circuit coupled to receive the refresh control signal from the control circuit and refreshing the refreshable memory to preserve data stored therein in response to the received refresh control signal;

an address generator generating an address;

an accessing circuit coupled to receive the generated address from the address generator and coupled to access data stored by the refreshable memory in response to the received address;

the processor coupled to the accessing circuit and processing data accessed by the accessing circuit; and

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address.

65. A memory system comprising:

a dynamic random access memory circuit storing data;

a control circuit generating a refresh control signal in response to processing of data by a processor to resolve contention between the processing of data by the processor and refreshing of the refreshable dynamic random access memory circuit by a refresh circuit;

the refresh circuit coupled to receive the refresh control signal from the control circuit and refreshing the dynamic random access memory circuit to preserve data stored therein in response to the received refresh control signal;

an address generator generating an address;

an accessing circuit coupled to receive the generated address from the address generator and coupled to access data stored by the dynamic random access memory circuit in response to the received address;

the processor coupled to the accessing circuit and processing data accessed by the accessing circuit; and

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the address.

66. A memory system comprising:

a dynamic random access memory storing data;

an address generator generating addresses;

an accessing circuit coupled to receive addresses from the address generator and to access data stored by the dynamic random access memory in response to the received addresses;

a processor coupled to the accessing circuit and processing data accessed by the accessing circuit; and

a plurality of detector circuits coupled to receive the addresses generated by the address generator and to generate a plurality of detector signals in response to the received addresses.

67. A memory system comprising:

a program memory storing a computer program;

a plurality of memories storing data;

an address generator generating addresses;

an accessing circuit coupled to receive addresses generated by the address generator and to access data stored by the plurality of memories in response to the received addresses;

a stored program computer coupled to the program memory and to the accessing circuit and processing data stored by the memories and accessed by the accessing circuit in response to the program stored by the program memory; and

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the generated addresses.

68. A memory system comprising:

a plurality of memories storing data;

an address generator generating addresses;

an accessing circuit coupled to receive addresses generated by the address generator and to the plurality of memories and accessing data stored by the memories in response to the received addresses;

a change detector circuit coupled to the address generator and generating a change detector signal in response to detection of a change in a first address generated by the address generator relative to a second address generated by the address generator;

a delay circuit coupled to receive the change detection signal from the change detector circuit and to the address generator and delaying generation of an address by the address generator in response to the received change detector signal;

a display processor coupled to the accessing circuit and processing the accessed data to generate display data; and

a display monitor coupled to receive the display data from the display processor and to display an image in response to the received display data.

69. A memory system comprising:

a plurality of memories storing data;

an address generator generating addresses;

an accessing circuit coupled to receive generated addresses from the address generator and access data stored by the memories in response to the received address;

a change detector circuit coupled to the address generator and generating a change detector signal in response to detection of a change in an address generated by the address generator;

a delay circuit coupled to receive the change detector signal from the change detector circuit, coupled to the address generator and delaying generation of an address by the address generator in response to the received change detector signal; and

an artificial intelligence processor coupled to the accessing circuit and processing the data accessed by the accessing circuit to generate artificial intelligence data.

70. A memory system comprising:

a plurality of memories storing data;

an address generator generating addresses;

an accessing circuit coupled to receive a generated address from the address generator and access data stored by the memories in response to the received address;

a change detector circuit coupled to the address generator and generating a change detector signal in response to detection of a selected change in a given address generated by the address generator relative to a previously generated address;

a delay circuit coupled to receive the change detector signal from the change detector circuit and coupled to delay generation of art address by the address generator in response to the change detector signal;

an image processor coupled to the accessing circuit and processing the data accessed by the accessing circuit to generate image display data; and

a display monitor coupled to the image processor and displaying an image in response to the image display data.

71. A memory system comprising:

a plurality of memories storing data;

an address generator generating an address;

an accessing circuit coupled to receive the address generated by the address generator and to access data stored by the memories in response to the received address;

a television image processor coupled to the accessing circuit and processing data accessed by the accessing circuit to generate television image data;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the generated address; and

a television monitor coupled to the television image processor and displaying a television image in response to the television image data.

72. A memory system comprising:

a plurality of memories storing data;

an address generator generating an address;

an accessing circuit coupled to receive the generated address from the address generator and to access data stored by the memories in response to the received address;

a plurality of detector circuits coupled to receive the generated address from the address generator and generating a plurality of detector signals in response to the received address;

a read only memory storing a computer program; and

a stored program computer coupled to the read only memory and to the accessing circuit and processing data stored by the memories and accessed by the accessing circuit in response to the program stored by the read only memory.

73. A memory system comprising:

a cache memory storing data;

a cache memory address generator generating cache memory addresses;

an accessing circuit coupled to receive cache memory addresses generated by the cache memory address generator and to access data stored by the cache memory in response to the received addresses;

a change detector circuit coupled to the cache memory address generator and generating a cache memory change detector signal in response to detection of a change in address generated by the cache memory address generator relative to another address generated by the cache memory address generator;

a cache memory delay circuit coupled to receive the change detector signal from the change detector circuit and coupled to control the cache memory address generator, the cache memory delay circuit delaying generation of a cache memory address by the cache memory address generator in response to the cache memory change detector signal; and

a processor coupled to the cache memory accessing circuit and processing the data accessed by the accessing circuit.

74. A memory system comprising:

a dynamic random access memory storing data;

an address generator generating addresses;

an accessing circuit coupled to receive addresses generated by the address generator, coupled to the dynamic random access memory and accessing data stored by the dynamic random access memory in response to the received addresses;

a processor coupled to the accessing circuit and processing data accessed by the accessing circuit;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the generated addresses, the detector signals defining different first and second states;

a scanout address update circuit coupled to respond to the detector signals from the plurality of detector circuits, coupled to the address generator and coupled to update the addresses generated by the address generator at a first address update rate in response to the first state of the detector signals; and

a re-addressing address update circuit coupled to respond to the detector signals from the plurality of detector circuits, coupled to the address generator and coupled to update the addresses generated by the address generator at a second address update rate that is lower than the first address update rate in response to the second state of the detector signals.

75. A memory system comprising:

a random access memory storing data;

an address generator generating addresses;

an accessing circuit coupled to receive addresses from the address generator, coupled to the random access memory and coupled to access data stored by the random access memory in response to the received addresses;

a processor coupled to the accessing circuit and processing data accessed by the accessing circuit;

a plurality of detector circuits coupled to the address generator and generating a plurality of detector signals in response to the generated addresses, the detector signals defining different first and second states;

an external scanout address update circuit coupled to respond to the detector signals from the plurality of detector circuits, coupled to the address generator and coupled to update the addresses generated by the address generator at a first address update rate in response to the first state of the detector signals; and

a re-addressing address update circuit coupled to respond to the detector signals from the plurality of detector circuits, coupled to the address generator and coupled to update the addresses generated by the address generator at a second address update rate that is lower than the first address update rate in response to the second state of the detector signals.

76. A memory system comprising:

a memory having a plurality of memory chips storing data;

an address generator circuit generating addresses, each address having less significant bits, middle significant bits, and more significant bits;

an accessing circuit coupled to the memory and to the address generator circuit and accessing data stored by the plurality of integrated circuit memory chips in response to generated addresses;

a first change detector circuit coupled to the address generator circuit and generating a first change detector signal in response to detection of a change in the more significant bits of an address generated by the address generator circuit relative to a previously generated address;

a second change detector circuit coupled to the address generator circuit and generating a second change detector signal in response to detection of a change in the middle significant bits of an address generated by the address generator circuit relative to a previously generated address;

a first delaying circuit coupled to the address generator circuit and to the first change detector circuit and delaying generating an address by the address generator circuit by a first delay period in response to the first change detector signal; and

a second delaying circuit coupled to the address generator circuit and to the second change detector circuit and delaying generating of an address by the address generator circuit by a second delay period that is different than the first delay period in response to the second change detector signal.