System for decoupling clock amortization from clock synchronization

• US 5,530,846 A
• Filed: 12/29/1993
• Issued: 06/25/1996
• Est. Priority Date: 12/29/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Strong, Hovey R.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/175,040
• Time in Patent Office: 909 Days
• Field of Search: 395/550
• US Class Current: 713/400
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock

Abstract

A method for accommodating frequent discrete clock synchronization adjustments while maintaining a continuous logical clock time that amortizes the adjustments at a predetermined rate. Two distinct logical clocks are used to decouple clock synchronization procedures from adjustment amortization procedures. One logical clock is discretely synchronized to an external time reference and a second logical clock is adjusted with amortization to provide a continuous monotonically non-decreasing logical clock time.

Claims

1. In a system including a hardware clock and plurality of logical clock objects, each logical clock object having a base rate, an amortization rate and a time with an offset relative to said hardware clock time, a computer implemented method for managing a first logical clock object of the plurality of logical clock objects, the first logical clock object having a first base rate, a first amortization rate, and a first logical clock object time with a first offset relative to said hardware clock time, said first logical clock time never differing by more than a predetermined deviation from a reference time, said method comprising the steps of:

(a) adjusting a second offset in a second logical clock object of the plurality of logical clock objects to synchronize a second logical clock object time to said reference clock time; and

(b) adjusting said first offset by amortizing an adjustment at said first amortization rate to synchronize said first logical clock object time to said second logical clock object time such that said first logical clock object time increases monotonically.

2. The method of claim 1, wherein said second adjusting step (b) comprises the additional steps of:

(b.1) comparing said hardware clock time to said first logical clock object time to determine whether said first offset includes all earlier said adjustments;

(b.2) if said first offset does not include all said earlier adjustments, halting said amortizing and

(b.3) adjusting said first offset by amortizing a cumulative adjustment at said first amortization rate to synchronize said first logical clock object time to said second logical clock object time, wherein said cumulative adjustment includes a portion of said earlier adjustments not yet amortized.

3. The method of claim 2 wherein said first logical clock object time increases continuously.

4. The method of claim 3, wherein said first adjusting step (a) comprises the additional steps of:

(a.1) setting a third base rate for a third logical clock object of the plurality of logical clock objects, the third base rate equal to an estimated difference between base rates of said hardware clock and said reference clock;

(a.2) adjusting a third offset to synchronize said third logical clock object time to said reference clock time; and

(a.3) adjusting said second offset to synchronize said second logical clock object time to said third logical clock object time.

5. The method of claim 2, wherein said first adjusting step (a) comprises the additional steps of:

(a.1) for a third logical clock object of the plurality of logical clock objects, setting a third base rate equal to an estimated difference between base rates of said hardware clock and said reference clock;

(a.2) adjusting a third offset to synchronize said third logical clock object time to said reference clock time; and

(a.3) adjusting said second offset to synchronize said second logical clock object time to said third logical clock object time.

6. The method of claim 1 wherein said first logical clock object time increases continuously.

7. The method of claim 1, wherein said first adjusting step (a) comprises the steps of:

(a.1) for a third logical clock object of the plurality of logical clock objects, setting a third base rate equal to an estimated difference between base rates of said hardware clock and said reference clock;

(a.2) adjusting a third offset to synchronize said third logical clock object time to said reference clock time; and

(a.3) adjusting said second offset to synchronize said second logical clock object time to said third logical clock object time.

8. The method of claim 1 further comprising the step of:

(c) adding to said first offset a discrete adjustment representing a political revision to said reference clock time, thereby synchronizing said first clock object time to an external political time.

9. A clock synchronization system for providing a smooth first logical clock time that never differs by more than a predetermined deviation from a reference clock time, said system comprising:

hardware clock means having a hardware clock rate for producing a hardware clock time;

first logical clock means having a first base rate and a first amortization rate for producing said first logical clock time;

second logical clock means having a second base rate coupled to said hardware clock means and to said first logical clock means for producing a second logical clock time having a first offset from said first logical clock time and a second offset from said hardware clock time;

synchronizing means coupled to said second logical clock means for adjusting said second offset to synchronize said second logical clock time to said reference clock time; and

amortizing means coupled to said first logical clock means for adjusting said first offset at said first amortization rate to synchronize said first logical clock time to said second logical clock time such that said first logical clock time increases monotonically.

10. The clock synchronization system of claim 9 wherein said amortizing means comprises:

comparing means for comparing said hardware clock time to said first logical clock time to determine whether said first offset includes all earlier said adjustments;

accumulating means coupled to said comparing means for adding the portion of said earlier adjustments not yet included in said first offset to a new adjustment to create a cumulative adjustment; and

restarting means coupled to said accumulating means for adjusting said first offset by said cumulative adjustment at said first amortization rate to synchronize said first logical clock time to said second logical clock time.

11. The clock synchronization system of claim 10 wherein said first logical clock time increases continuously.

12. The clock synchronization system of claim 11 further comprising:

third logical clock means coupled to said hardware clock means for producing a third logical clock time having a third base rate;

drift compensation means coupled to said third logical clock means for setting said third base rate equal to an estimated difference between said hardware clock rate and the base rate of said reference clock; and

estimation means coupled to said second logical clock means and to said third logical clock means for adjusting said second offset to synchronize said second logical clock time to said third logical clock time.

13. The clock synchronization system of claim 10 further comprising:

third logical clock means coupled to said hardware clock means for producing a third logical clock time having a third base rate;

drift compensation means coupled to said third logical clock means for setting said third base rate equal to an estimated difference between said hardware clock rate and the base rate of said reference clock; and

estimation means coupled to said second logical clock means and to said third logical clock means for adjusting said second offset to synchronize said second logical clock time to said third logical clock time.

14. The clock synchronization system of claim 9 wherein said first logical time increases continuously.

15. The clock synchronization system of claim 9 further comprising:

third logical clock means coupled to said hardware clock means for producing a third logical clock time having a third base rate;

drift compensation means coupled to said third logical clock means for setting said third base rate equal to an estimated difference between said hardware clock rate and the base rate of said reference clock; and

estimation means coupled to said second logical clock means and to said third logical clock means for adjusting said second offset to synchronize said second logical clock time to said third logical clock time.

16. The clock synchronization system of claim 9 further comprising:

political adjustment means coupled to said first logical clock means for adding a discrete adjustment to said first offset representing a political revision to said reference clock time, thereby synchronizing said first logical clock time to an external political time.

17. The clock synchronization system of claim 9 wherein said synchronizing means is for the discrete adjustment of said second offset without amortization.

18. A computer-implemented clock comprising:

a hardware clock for producing a hardware clock time signal T_H ;

means for storing a plurality of logical clock data objects, each said logical clock data object including

a time signal value T_L,

an offset ADD to said hardware clock time signal T_H,

an amortization rate aRATE having a value in the interval,

a base rate cRATE of increase in said time value T_L,

an adjustment ADJ to said offset ADD to be amortized,

a bit SIGN representing the sign of said adjustment ADJ,

a beginning amortization time aBEGIN,

an ending amortization time tEND,

a multiplier MULT of said time value T_H during amortization, and

an unamortized adjustment amount DIFF remaining during amortization; and

means for producing said logical clock time signal T_L =MULT*T_H +DIFF if said hardware clock time signal T_H <

tEND and for producing said logical clock time signal T_L =cRATE*T_H +ADD+ADJ otherwise.

19. The computer-implemented clock of claim 18 further comprising:

means for initializing said each logical clock data object such that

said ending amortization time tEND=T_H,

said beginning amortization time aBEGIN=T_H *cRATE,

said adjustment ADJ=0.0,

said bit SIGN=1,

said multiplier MULT=cRATE(aRATE*SIGN)), and

said difference DIFF=ADD-(aBEGIN*aRATE*SIGN).